參數(shù)資料
型號: CY7C67200
廠商: Cypress Semiconductor Corp.
英文描述: EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機/外圍設(shè)備控制器)
中文描述: 的EZ - OTG公司可編程的USB On - The - Go的主機/外設(shè)控制器(的EZ - OTG公司可編程的USB On - The - Go的主機/外圍設(shè)備控制器)
文件頁數(shù): 59/82頁
文件大小: 1719K
代理商: CY7C67200
CY7C67200
Document #: 38-08014 Rev. *F
Page 59 of 82
Receive Data Ready
(Bit 8)
The Receive Data Ready bit is a read only bit that indicates if the receive port has data ready.
1:
Receive port has data ready to read
0:
Receive port does not have data ready
Transmit Empty
(Bit 7)
The Transmit Empty bit is a read only bit that indicates if the transmit FIFO is empty.
1:
Transmit FIFO is empty
0:
Transmit FIFO is not empty
Receive Full
(Bit 6)
The Receive Full bit is a read only bit that indicates if the receive FIFO is full.
1:
Receive FIFO is full
0:
Receive FIFO is not full
Transmit Bit Length
(Bits [5:3])
The Transmit Bit Length field controls whether a full byte or partial byte is to be transmitted. If Transmit Bit Length is ‘000’, a full
byte is transmitted. If Transmit Bit Length is ‘001’ to ‘111’, the value indicates the number of bits that will be transmitted.
Receive Bit Length
(Bits [2:0])
The Receive Bit Length field controls whether a full byte or partial byte will be received. If Receive Bit Length is ‘000’ then a full
byte will be received. If Receive Bit Length is ‘001’ to ‘111’, then the value indicates the number of bits that will be received.
8.10.3
SPI Interrupt Enable Register [0xC0CC] [R/W]
Figure 8-67. SPI Interrupt Enable Register
Register Description
The SPI Interrupt Enable register controls the SPI port.
Receive Interrupt Enable
(Bit 2)
The Receive Interrupt Enable bit enables or disables the byte mode receive interrupt (RxIntVal).
1:
Enable byte mode receive interrupt
0:
Disable byte mode receive interrupt
Transmit Interrupt Enable
(Bit 1)
The Transmit Interrupt Enable bit enables or disables the byte mode transmit interrupt (TxIntVal).
1:
Enables byte mode transmit interrupt
0:
Disables byte mode transmit interrupt
Transfer Interrupt Enable
(Bit 0)
The Transfer Interrupt Enable bit enables or disables the block mode interrupt (XfrBlkIntVal).
1:
Enables block mode interrupt
0:
Disables block mode interrupt
Bit #
15
14
13
12
11
10
9
8
Field
Reserved...
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Reserved
Receive
Interrupt Enable
Transmit
Interrupt Enable
Interrupt Enable
Read/Write
-
-
-
-
-
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
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