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參數(shù)資料
| 型號： | CY7C67200 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機(jī)/外圍設(shè)備控制器) |
| 中文描述： | 的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外設(shè)控制器（的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外圍設(shè)備控制器） |
| 文件頁數(shù)： | 46/82頁 |
| 文件大?。?/td> | 1719K |
| 代理商： | CY7C67200 |
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CY7C67200
Document #: 38-08014 Rev. *F
Page 46 of 82
Register Description
The HSS Control register provides high-level status and
control over the HSS port.
HSS Enable
(Bit 15)
The HSS Enable bit enables or disables HSS operation.
1:
Enables HSS operation
0:
Disables HSS operation
RTS Polarity Select
(Bit 14)
The RTS Polarity Select bit selects the polarity of RTS.
1:
RTS is true when LOW
0:
RTS is true when HIGH
CTS Polarity Select
(Bit 13)
The CTS Polarity Select bit selects the polarity of CTS.
1:
CTS is true when LOW
0:
CTS is true when HIGH
XOFF
(Bit 12)
The XOFF bit is a read only bit that indicates if an XOFF has
been received. This bit is automatically cleared when an XON
has been received.
1:
XOFF received
0:
XON received
XOFF Enable
(Bit 11)
The XOFF Enable bit enables or disables XON/XOFF software
handshaking.
1:
Enable XON/XOFF software handshaking
0:
Disable XON/XOFF software handshaking
CTS Enable
(Bit 10)
The CTS Enable bit enables or disables CTS/RTS hardware
handshaking.
1:
Enable CTS/RTS hardware handshaking
0:
Disable CTS/RTS hardware handshaking
Receive Interrupt Enable
(Bit 9)
The Receive Interrupt Enable bit enables or disables the
Receive Ready and Receive Packet Ready interrupts.
1:
Enable the Receive Ready and Receive Packet Ready
interrupts
0:
Disable the Receive Ready and Receive Packet Ready
interrupts
Done Interrupt Enable
(Bit 8)
The Done Interrupt Enable bit enables or disables the Transmit
Done and Receive Done interrupts.
1:
Enable the Transmit Done and Receive Done interrupts
0:
Disable the Transmit Done and Receive Done interrupts
Transmit Done Interrupt Flag
(Bit 7)
The Transmit Done Interrupt Flag bit indicates the status of the
Transmit Done Interrupt. It will set when a block transmit is
finished. To clear the interrupt, a ‘1’ must be written to this bit.
1:
Interrupt triggered
0:
Interrupt did not trigger
Receive Done Interrupt Flag
(Bit 6)
The Receive Done Interrupt Flag bit indicates the status of the
Receive Done Interrupt. It will set when a block transmit is
finished. To clear the interrupt, a ‘1’ must be written to this bit.
1:
Interrupt triggered
0:
Interrupt did not trigger
One Stop Bit
(Bit 5)
The One Stop Bit bit selects between one and two stop bits for
transmit byte mode. In receive mode, the number of stop bits
may vary and does not need to be fixed.
1:
One stop bit
0:
Two stop bits
Transmit Ready
(Bit 4)
The Transmit Ready bit is a read only bit that indicates if the
HSS Transmit FIFO is ready for the CPU to load new data for
transmission.
1:
HSS transmit FIFO ready for loading
0:
HSS transmit FIFO not ready for loading
Packet Mode Select
(Bit 3)
The Packet Mode Select bit selects between Receive Packet
Ready and Receive Ready as the interrupt source for the
RxIntr interrupt.
1:
Selects Receive Packet Ready as the source
0:
Selects Receive Ready as the source
Receive Overflow Flag
(Bit 2)
The Receive Overflow Flag bit indicates if the Receive FIFO
overflowed when set. This flag can be cleared by writing a ‘1’
to this bit.
1:
Overflow occurred
0:
Overflow did not occur
Receive Packet Ready Flag
(Bit 1)
The Receive Packet Ready Flag bit is a read only bit that
indicates if the HSS receive FIFO is full with eight bytes or not.
1:
HSS receive FIFO is full
0:
HSS receive FIFO is not full
Receive Ready Flag
(Bit 0)
The Receive Ready Flag is a read only bit that indicates if the
HSS receive FIFO is empty or not.
1:
HSS receive FIFO is not empty (one or more bytes is
reading for reading)
0:
HSS receive FIFO is empty
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C672001-48BAXI | 功能描述:8位微控制器 -MCU CY7C672001-48BAXI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C672001-48BAXIT | 功能描述:8位微控制器 -MCU CY7C672001-48BAXIT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C67200-48BAXI | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67200-48BAXIT | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67300-100AI | 制造商:Cypress Semiconductor 功能描述:INTERFACE MISC |
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