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參數(shù)資料
| 型號： | BX80530C1400512 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA370 |
| 封裝： | FLIP CHIP, PGA-370 |
| 文件頁數(shù)： | 90/94頁 |
| 文件大?。?/td> | 1775K |
| 代理商： | BX80530C1400512 |
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82
Datasheet
Intel Pentium III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
RESET#
I
Asserting the RESET# signal resets all processors to known states and invalidates
their L1 and L2 caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least one millisecond after VCCCORE and
CLK have reached their proper specifications. On observing active RESET#, all
processor system bus agents will deassert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
P6 Family of Processors Hardware Developer’s Manual for details.
The processor may have its outputs tristated via power-on configuration. Otherwise,
if INIT# is sampled active during the active-to-inactive transition of RESET#, the
processor will execute its Built-in Self-Test (BIST). Whether or not BIST is
executed, the processor will begin program execution at the power on Reset vector
(default 0_FFFF_FFF0h). RESET# must connect the appropriate pins of all
processor system bus agents.
RESET# is the only AGTL signal which does not have on-die termination.
Therefore, it is necessary to place a discrete 56
resistor to V
TT. Refer to the
platform design guide for implementation detail and resistor tolerance.
RESET2#
I
RESET2# pin is provided to differentiate the Intel Pentium III processor with
512KB L2 Cache from legacy Pentium III processors. The Intel Pentium III
processor with 512KB L2 Cache. does not use the RESET2# pin. Refer to the
platform design guide for the proper connections of this signal.
RP#
I/O
The RP# (Request Parity) signal is driven by the request initiator, and provides
parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of
all processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. This definition allows parity to be high
when all covered signals are high.
RS[2:0]#
I/O
The RS[2:0]# (Response Status) signals are driven by the response agent (the
agent responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
RSP#
I
The RSP# (Response Parity) signal is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of RS[2:0]#,
the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
RTTCTRL
I
The RTTCTRL input signal provides AGTL termination control. The Intel
Pentium III processor with 512KB L2 Cache samples this input to set the
termination resistance value for the on-die AGTL termination. This signal must be
connected to a 56
resistor to Vss on a uni-processor platform or a 68 resistor to
Vss on a dual-processor platform. Refer to the platform design guide for
implementation detail and resistor tolerance.
SLEWCTRL
I
The SLEWCTRL input signal provides AGTL slew rate control. The Intel
Pentium III processor with 512KB L2 Cache samples this input to determine the
slew rate for AGTL signals when it is the driving agent. This signal must be
connected to a 110
resistor to Vss. Refer to the platform design guide for
implementation detail and resistor tolerance.
SLP#
I
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
Table 37. Signal Description (Sheet 7 of 9)
Name
Type
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX80530F1100256 | 制造商:Intel 功能描述:CELERON PROCESSOR - Boxed Product (Development Kits) |
| BX80530F1200256 | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 64-BIT 0.13UM 1.2GHZ 370-PIN FCPGA2 - Boxed Product (Development Kits) |
| BX80530F1300256 | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 64-BIT 0.13UM 1.3GHZ 370-PIN FCPGA2 - Boxed Product (Development Kits) |
| BX80530F1400256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| BX80531NK170G | 制造商:Intel 功能描述:MPU PENTIUM 4 PROCESSOR NETBURST 64-BIT 0.18UM 1.7GHZ - Boxed Product (Development Kits) 制造商:Intel 功能描述:P4 Socket 478 1.7GHz with fan |
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