參數(shù)資料
型號(hào)： BX80530C1400512
廠(chǎng)商： INTEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA370
封裝： FLIP CHIP, PGA-370
文件頁(yè)數(shù)： 42/94頁(yè)
文件大?。?/td> 1775K
代理商： BX80530C1400512
Datasheet
39
Intel Pentium III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
7. A negative value for
ρ indicates that the amplitude of ringback is above V
REF. (i.e., φ = -100 mV specifies the
signal cannot ringback below VREF + 100 mV).
8.
φ and ρ: are measured relative to V
REF. α: is measured relative to VREF + 200 mV.
3.3
AGTL Signal Quality Specifications and Measurement
Guidelines
3.3.1
Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast
signal edge rates. The processor can be damaged by repeated overshoot events on 1.25 V or 2.5 V
tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). Determining
the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse
direction and the activity factor (AF). Permanent damage to the processor is the likely result of
excessive overshoot/undershoot. Violating the overshoot/undershoot guideline will also make
satisfying the ringback specification difficult.
When performing simulations to determine impact of overshoot and undershoot, ESD diodes must
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot or undershoot protection. ESD diodes modeled within Intel I/O buffer models do not
clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models
are being used to characterize the Intel Pentium III processor with 512KB L2 Cache
performance, care must be taken to ensure that ESD models do not clamp extreme voltage levels.
Intel I/O buffer models also contain I/O capacitance characterization. Therefore, removing the ESD
diodes from an I/O buffer model will impact results and may yield excessive overshoot/undershoot.
Figure 19. Low to High AGTL Receiver Ringback Tolerance
0.7V Clk Ref
Clock
Time
V
start
V
REF - 0.2
V
REF
V
REF + 0.2
Note: High to low case is analogous
τ
α
δ
ρ
φ
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