參數(shù)資料
型號(hào)： BX80530C1400512
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA370
封裝： FLIP CHIP, PGA-370
文件頁數(shù)： 33/94頁
文件大?。?/td> 1775K
代理商： BX80530C1400512
Datasheet
31
Intel Pentium III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
NOTES:
1. All signals, during their invalid states, must be guarded against spurious levels from effecting the platform
during processor power-up sequence.
2. Configuration Input signals include: A[14:5], BR0#, BR1#, INIT#. For timing of these signals, please refer to
Notes: For Figure 9 through Figure 19, the following apply:
1. Figure 9 through Figure 19 are to be used in conjunction with Table 13 through Table 19.
2. All timings for the AGTL signals at the processor pins are referenced to the rising edge of
BCLK and the falling edge of BCLK# at the crossing point for differential clock mode and to
the rising edge of BCLK at BCLKVREF (1.25V) for single-ended clock mode. All AGTL signal
timings (address bus, data bus, etc.) are referenced at 2/3 of VTT at the processor pins.
3. All timings for the APIC I/O signals at the processor pins are referenced to the PICCLK rising
edge at 0.9 V. All APIC I/O signal timings are referenced at 1.0 V at the processor pins.
4. All timings for the TAP signals at the processor pins are referenced to the TCK rising edge at
1.0 V. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.0 V at the processor pins.
Table 20. Platform Power-On Timings2
T# Parameter
Min
Max
Unit
Figure
Notes
T45: Valid Time Before VTT_PWRGD
1.0
mS
1
T46: Valid Time Before PWRGOOD
2.0
mS
1
T47: RESET# Inactive to Valid Outputs
1
BCLK
1
T48: RESET# Inactive to Drive Signals
4
BCLK
1
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