參數(shù)資料
型號(hào)： BX80530C1400512
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA370
封裝： FLIP CHIP, PGA-370
文件頁(yè)數(shù)： 41/94頁(yè)
文件大小： 1775K
代理商： BX80530C1400512
38
Datasheet
Intel Pentium III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
3.2
AGTL Signal Quality Specifications and Measurement
Guidelines
Many scenarios have been simulated to generate a set of AGTL layout guidelines which are
available in the appropriate platform design guide. Refer to the Intel
Pentium II Processor
Developer’s Manual (Order Number 243502) for the AGTL buffer specification.
Table 23 provides the AGTL signal quality specifications for the processor for use in simulating
signal quality at the processor pins.
The Intel Pentium III processor with 512KB L2 Cache maximum allowable overshoot and
undershoot specifications for a given duration of time are detailed in Table 22 through Table 24.
Figure 19 shows the AGTL ringback tolerance and Figure 20 shows the overshoot/undershoot
waveform.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors with 512KB L2
cache at all frequencies.
2. Specifications are for the edge rate of 0.3 - 3V/ns. See Figure 19 for the generic waveform.
3. All values specified by design characterization.
4. Please see Table 22 for maximum allowable overshoot.
5. Ringback between VREF + 100 mV and VREF + 200 mV or VREF - 300 mV and VREF - 100 mVs requires the
flight time measurements to be adjusted as described in the Intel AGTL Specifications. Ringback below VREF
+ 100 mV or above VREF - 100 mV is not supported.
6. Intel recommends simulations not exceed a ringback value of VREF ±200 mV to allow margin for other
sources of system noise.
Figure 18. BCLK/BCLK#, PICCLK Generic Clock Waveform at the Processor Pins
V2
V1
V3
V4
V5
Table 23. AGTL Signal Groups Ringback Tolerance Specifications at the Processor
Pins 1, 2, 3
T# Parameter
Min
Unit
Figure
Notes
α: Overshoot
100
mV
4, 8
τ: Minimum Time at High
0.50
ns
ρ: Amplitude of Ringback
±200
mV
5, 6, 7, 8
φ: Final Settling Voltage
200
mV
8
δ: Duration of Squarewave Ringback
N/A
ns
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