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參數(shù)資料
| 型號： | BX80530C1400512 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA370 |
| 封裝： | FLIP CHIP, PGA-370 |
| 文件頁數(shù)： | 5/94頁 |
| 文件大?。?/td> | 1775K |
| 代理商： | BX80530C1400512 |
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Datasheet
5
Intel Pentium III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
2.0
Electrical Specifications
2.1
Processor System Bus and VREF
The Intel Pentium III processor with 512KB L2 Cache uses the original low voltage signaling
of the Gunning Transceiver Logic (GTL) technology for the system bus. The GTL system bus
operates at 1.25V signal levels versus GTL+ which operates at 1.5V signal levels. The GTL+ signal
technology is used by the Intel Pentium Pro, Intel Pentium II and legacy
Intel Pentium III processors.
Current P6 family processors vary from the Intel Pentium Pro processor in their output buffer
implementation. The buffers that drive the system bus signals on the Intel Pentium III processor
with 512KB Cache are actively driven to VTT for one clock cycle after the low to high transition to
improve rise times. These signals are open-drain and require termination to a supply. Because this
specification is different from the standard GTL specification, it is referred to as AGTL, or Assisted
GTL in this and other documentation related to the Intel Pentium III processor.
AGTL logic and AGTL+ logic are not compatible with each other due to differences with the signal
switching levels. Intel Pentium III processors with 512KB L2 Cache cannot be installed into
platforms where the chipset only supports the AGTL+ signal levels. For more information on
AGTL or AGTL+ routing, please refer to the appropriate platform design guide.
AGTL inputs use differential receivers which requires a reference voltage (VREF). VREF is used by
the differential receivers to determine if the input signal is a logical 0 or a logical 1. The VREF
signal is typically implemented as a voltage divider on the platform. Noise decoupling is critical for
the VREF signal. Refer to the platform design guide for the recommended decoupling requirements.
Another important item for the AGTL system bus is termination.
System bus termination is used to pull each signal to a high voltage level and to control reflections
on the transmission line. The processor contains on-die termination resistors that provide
termination for one end of the system bus.
The other end of the system bus should also be
terminated near the chipset by resistors placed on the platform or on-die termination within the
chipset. It is recommended that the system bus is implemented using Dual-End Termination
(DET) to meet the timings and signal integrity specified by the Intel Pentium III processor with
512KB L2 Cache. Figure 2 is a schematic representation of the AGTL bus topology for the Intel
Pentium III processor with 512KB L2 Cache, when the chipset does not have on-die termination.
Note:
The RESET# signal requires a discrete external termination resistor on the system board.
Note:
The AGTL bus depends on incident wave switching. Therefore, timing calculations for AGTL
signals are based on flight time as opposed to capacitive deratings. Analog signal simulations of the
system bus, including trace lengths, is highly recommended especially when not following the
recommended layout guidelines.
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相關代理商/技術參數(shù) |
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| BX80530F1300256 | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 64-BIT 0.13UM 1.3GHZ 370-PIN FCPGA2 - Boxed Product (Development Kits) |
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| BX80531NK170G | 制造商:Intel 功能描述:MPU PENTIUM 4 PROCESSOR NETBURST 64-BIT 0.18UM 1.7GHZ - Boxed Product (Development Kits) 制造商:Intel 功能描述:P4 Socket 478 1.7GHz with fan |
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