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參數(shù)資料
| 型號： | BX80530C1400512 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA370 |
| 封裝： | FLIP CHIP, PGA-370 |
| 文件頁數(shù)： | 11/94頁 |
| 文件大?。?/td> | 1775K |
| 代理商： | BX80530C1400512 |
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Datasheet
11
Intel Pentium III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
2.4
Decoupling Guidelines
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. The fluctuations can
cause voltages on power planes to sag below their nominal values if bulk decoupling is not
adequate. Care must be taken in the board design to ensure that the voltage provided to the
processor remains within the specifications listed in Table 7. Failure to do so can result in timing
violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a
voltage overshoot).
2.4.1
Processor VCC
CORE Decoupling
The regulator for the VCCCORE input must be capable of delivering the dICCCORE/dt (defined in
Table 7) while maintaining the required tolerances (also defined in Table 7). Failure to meet these
specifications can result in timing violations (during VCCCORE sag) or a reduced lifetime of the
component (during VCCCORE overshoot).
The processor requires both high frequency and bulk decoupling on the system motherboard for
proper AGTL bus operation. The minimum recommendation for the processor decoupling
requirement is listed below. All capacitors should be placed next to and within the PGA370 socket
cavity and mounted on the primary side of the motherboard. The capacitors are arranged to
minimize the overall inductance between the VCCCORE and Vss power pins.
Decoupling Recommendations:
1) VCCCORE decoupling - A minimum of sixteen 4.7uF capacitors in a 1206 package.
2) VTT decoupling - Twenty 0.1uF capacitors in 0603 packages.
3) VREF decoupling - 0.1uF and 0.001uF capacitors in 0603 package placed near the VREF pins.
For additional decoupling requirements, please refer to the appropriate platform design guide for
recommended capacitor component value/quantity and placement.
2.5
Processor System Bus Clock and Processor Clocking
The Intel Pentium III processor with 512KB L2 Cache will implement an auto-detect
mechanism that will allow the processor to use either single-ended or differential signaling for the
system bus and processor clocking. The processor checks to see if the signal on pin Y33 is
toggling. If this signal is toggling then the processor operates in differential mode. Refer to Figure
5 for an example on differential clocking. Resistor values and clock topology are listed in the
appropriate platform design guide for a differential implementation. Note: References to BCLK
throughout this document will also imply to it’s complement signal, BCLK# in differential
implementations, and when noted otherwise.
The BCLK input directly controls the operating speed of the system bus interface. All AGTL
system bus timing parameters are specified with respect to the crossing point of the rising edge of
the BCLK and the falling edge of BCLK# inputs in a differential implementation. See the
P6 Family of Processors Hardware Developer’s Manual for further details. The reference voltage
of the BCLK in the P6 Family of Processors Hardware Developer Manual is re-defined as the
crossing point of the BCLK and BCLK# in a differential implementation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| BX80530F1100256 | 制造商:Intel 功能描述:CELERON PROCESSOR - Boxed Product (Development Kits) |
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| BX80530F1300256 | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 64-BIT 0.13UM 1.3GHZ 370-PIN FCPGA2 - Boxed Product (Development Kits) |
| BX80530F1400256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| BX80531NK170G | 制造商:Intel 功能描述:MPU PENTIUM 4 PROCESSOR NETBURST 64-BIT 0.18UM 1.7GHZ - Boxed Product (Development Kits) 制造商:Intel 功能描述:P4 Socket 478 1.7GHz with fan |
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