參數(shù)資料
型號(hào)： BX80530C1400512
廠商： INTEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA370
封裝： FLIP CHIP, PGA-370
文件頁(yè)數(shù)： 21/94頁(yè)
文件大?。?/td> 1775K
代理商： BX80530C1400512
20
Datasheet
Intel Pentium III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
2. All specifications in this table apply only to the Intel Pentium III processor with 512KB L2 Cache.
3. VccCORE and IccCORE supply the processor core and the on-die L2 cache.
4. VTT must be held to 1.25V ±9% while the AGTL bus is active. It is required that VTT be held to 1.25V ±3%
while the processor system bus is static (idle condition). The ±3% range is the required design target; ±9%
will come from the transient noise added. This is measured at the PGA370 socket pins on the bottom side of
the baseboard.
5. These are the tolerance requirements, across a 20 MHz frequency bandwidth, measured at the processor
socket pin on the soldered-side of the motherboard. VCCCORE must return to within the static voltage
specification within 100
s after a transient event; see the VRM 8.5 DC-DC Converter Design Guidelines for
further details.
6. Maximum ICC is measured at VCC typical voltage and under a maximum signal loading conditions.
7. The current specified is also for AutoHALT state.
8. Maximum values are specified by design/characterization at nominal VccCORE.
9. Based on simulation and averaged over the duration of any change in current. Use to compute the maximum
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
10.dIcc/dt specifications are measured and specified at the PGA370 socket pins.
11. Static voltage regulation includes: DC output initial voltage set point adjust, Output ripple and noise, Output
load ranges specified in the tables above. See VRM 8.5 DC-Dc Converter Design Guidelines.
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