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參數(shù)資料
| 型號： | BX80530C1400512 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA370 |
| 封裝： | FLIP CHIP, PGA-370 |
| 文件頁數(shù)： | 30/94頁 |
| 文件大小： | 1775K |
| 代理商： | BX80530C1400512 |
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28
Datasheet
Intel Pentium III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
4. Valid delay timings for these signals are specified into 50
to 1.25V, V
REF at 0.8 V ±2% and with 56 or
68
on-die R
TT.
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. Specification is for a minimum 0.40 V swing from VREF - 200 mV to VREF + 200 mV. This assumes an edge
rate of 0.3V/ns.
8. Specification is for a maximum 0.8 V swing from VTT - 0.8V to VTT. This assumes an edge rate of 3V/ns.
9. This should be measured after VCCCORE, VTT, VccCMOS, and BCLK (and BCLK#) are stable
10.BREQ signals observe a 1.2nS minimum setup time.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors with 512KB L2
cache at all frequencies
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. All CMOS outputs shall be asserted for at least 2 system bus clocks.
5. When driven inactive or after VCCCORE, VTT, VCCCMOS, and BCLK and BCLK# are stable.
Table 16. System Bus Timing Specifications (CMOS Signal Group) 1, 2, 3, 4
T# Parameter
Min
Max
Unit
Figure
Notes
T14: CMOS Input Pulse Width, except
PWRGOOD
2BCLKs
Active and
Inactive states
T15: PWRGOOD Inactive Pulse Width
10
BCLKs
5
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