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參數(shù)資料
| 型號(hào)： | BX80530C1400512 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA370 |
| 封裝： | FLIP CHIP, PGA-370 |
| 文件頁數(shù)： | 26/94頁 |
| 文件大?。?/td> | 1775K |
| 代理商： | BX80530C1400512 |
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24
Datasheet
Intel Pentium III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
2.11
AGTL System Bus Specifications
It is recommended that the AGTL bus be routed in a daisy-chain fashion with termination resistors
to VTT. These termination resistors are placed electrically between the ends of the signal traces and
the VTT voltage supply. The valid high and low levels are determined by the input buffers using a
reference voltage called VREF. Refer to the appropriate platform design guide for more information
reference voltage (VREF) is generated on the system motherboard and should be set to 2/3 VTT for
the processor and other AGTL logic. It is important that the baseboard impedance be specified and
held to a ±15% tolerance, and that the intrinsic trace capacitance for the AGTL signal group traces
is known and well-controlled. For more details on the AGTL buffer specification, see the
Intel
Pentium II Processor Developer’s Manual and AP-585, Intel Pentium II Processor
AGTL Guidelines.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors with 512KB L2
cache at all frequencies.
2. Intel Pentium III processors with 512KB L2 cache for the PGA370 socket contain AGTL termination
resistors on the processor die, except for the RESET# input.
3. VTT must be held to 1.25V ±9%. It is required that VTT be held to 1.25V ±3% while the processor system bus
is idle (static condition). This is measured at the PGA370 socket pins on the bottom side of the baseboard.
4. Uni-processor platforms require a 56
resistor and dual-processor platforms require a 68 resistor.
Tolerance for on-die Rtt is +/-10% (56, 68
resistors). Rtt is +/-15% (100 resistors).
5. VREF is generated on the motherboard and should be 2/3 VTT ±5% nominally. Ensure that there is adequate
VREF decoupling on the motherboard.
2.12
System Bus Timing Specifications
The processor system bus timings specified in this section are defined at the socket pins on the
bottom of the motherboard. Unless otherwise specified, timings are tested at the processor pins
during manufacturing. Timings at the processor pins are specified by design characterization. See
Section 7.0 for the processor signal definitions.
Table 11. 3.3 Volt CMOS Output Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
V
Nominal Voltage
3.45
V
3.3 + 5%
VOH
Output High Voltage
0.9
V
ILO
Output Leakage Current
100
A
Table 12. Processor AGTL Bus Specifications 1, 2
Symbol
Parameter
Min
Typ
Max
Units
Notes
VTT
Bus Termination Voltage
1.1375
1.25
V
3
On-die RTT
Termination Resistor
50
56
68
115
4
VREF
Bus Reference Voltage
2/3VTT
V5
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