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| 型號： | 5962D1022901QXC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 7/68頁 |
| 文件大?。?/td> | 1475K |
| 代理商： | 5962D1022901QXC |
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15
CAS Latency (CL)
CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data.
The latency can be set to two or three clocks.
If a READ command is registered at clock edge n and the latency is m clocks, the data will be available by clock edge n + m. The
DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, as shown in Figure 5, assuming that the clock cycle time is such that all
relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs start
driving after T1 and the data will be valid by T2. Table 4 indicates the operating frequencies at which each CL setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Table 4. CAS Latency
Allowable Operating Frequency (MHz)
Frequency
Latency
< 100
CL = 2
Figure 5: CAS Latency
READ
NOP
Data
T3
T2
T1
T0
tOH
tAC
tLZ
CL = 2
CLK
Command
DQ
READ
NOP
Data
T3
T2
T1
T0
tOH
tAC
tLZ
CL = 3
CLK
DQ
NOP
Command
Don’t Care
Undefined
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