參數(shù)資料
型號： 5962D1022901QXC
元件分類： DRAM
英文描述： 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128
封裝： CERAMIC, QFP-128
文件頁數(shù)： 36/68頁
文件大?。?/td> 1475K
代理商： 5962D1022901QXC
41
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto
precharge disabled.
8. Concurrent auto precharge: Bank n initiates the auto precharge command when its burst has been interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m interrupts the READ on bank n, CL later
(Figure 10).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m interrupts the READ on bank n when
registered (Figure 12 and Figure 13). DQM should be used one clock prior to the WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank minterrupst the WRITE on bank n when
registered (Figure 20), with the data-out appearing CL later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m interrupts the WRITE on bank n when
registered (Figure 18). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank minterrupts the READ on bank n, CL later. The
PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 27).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m interrupts the READ on bank n when
registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE
to bank m is registered (Figure 28).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank minterrupts the WRITE on bank n when
registered, with the data-out appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is
registered. The last valid WRITE to bank n will be datain registered one clock prior to the READ to bank m (Figure 29).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank minterrups the WRITE on bank n when
registered. The PRECHARGE to bank n begins after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n
will be data registered one clock prior to the WRITE to bank m (Figure30).
相關(guān)PDF資料
PDF描述
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5962F0052301QXC 制造商:Intersil Corporation 功能描述:
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