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參數(shù)資料
| 型號： | 5962D1022901QXC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 41/68頁 |
| 文件大小： | 1475K |
| 代理商： | 5962D1022901QXC |
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46
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019,
Condition A up to the maximum TID level procured.
1. All voltages referenced to VSS.
2. Measured only for initial qualification and after process or design change that could affect this parameter.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.
4. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range
(–40°C ≤ TC ≤ 105°C) is ensured.
5. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ
must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the
tREF refresh requirement is exceeded.
6. AC characteristics assume tT = 1ns, supplied as a design limit, neither tested nor guaranteed.
7. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
8. Outputs measured at 1.5V with equivalent load:
9. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5Vcrossover point. If the input transition time is longer than 1ns, then the
timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point.
10. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels.
11. IDD specifications are tested after the device is properly initialized.
12. The IDD current will increase or decrease in a proportional amount by the amount the frequency is altered for the test condition.
13. Address transitions average one transition every two clocks.
14. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate.
15. CL = 2, tCK = 7.5ns.
16. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value.
VDD
DUT
Zo = 50-ohms
VDD
CL = 40pF
RTERM
100-ohms
Test
Point
RTERM
100-ohms
Equivalent Test Load Circuit
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