- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄293971 > 5962D1022901QXC 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128 PDF資料下載
參數(shù)資料
| 型號： | 5962D1022901QXC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 3/68頁 |
| 文件大?。?/td> | 1475K |
| 代理商： | 5962D1022901QXC |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
11
FUNCTIONAL DESCRIPTION
The 2.5G and 3.0G SDRAMs are organized as 16M x 40 x 4 banks and 16M x 48 x 4 banks that operate on 3.3V using a synchronous
interface (signals are registered on the positive CLK edge). Read and write accesses to the SDRAM are burst oriented. Accesses start
at address locations selected and continue for programmed number of locations in a programmed sequence. Device accesses start
with the registration of the ACTIVE command followed by a READ or WRITE command. Some address and both bank bits are reg-
istered coincident to the ACTIVE command registration and are used to select the row and bank locations, while column location to
initiate burst access address bits A0-A9 are registered at time of READ/WRITE command.
Previous to normal operation the device must initialized properly.
Initialization
The SDRAMs must be powered up and initialized in a certain manner. Failure to initial devices may result in unpredictable behavior.
Once stable power is applied to VDD and VDDQ (simultaneously), and the clock is running and stable (cycling within specified pa-
rameters) the device requires a minimum 100
μs delay prior to issuing any command other than NOP or COMMAND INHIBIT. At
some time during this period the COMMAND INHIBIT or NOP can be issued and should continue through the end of the 100
μs
period. After the delay has been completed with at least one COMMAND INHIBIT or NOP command, a PRECHARGE command
should be applied. All banks must then be precharged, thereby placing all banks in the device into the idle state. Once in the idle state,
two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode
register programming. Because the mode register powers up in an unknown state, it should be loaded prior to applying any opera-
tional command.
The recommended power-up sequence for SDRAMs:
1. Simultaneously apply power to VDD and VDDQ.
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-compatible.
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing constraints specified for the clock pin.
4. Wait at least 100
μs prior to issuing any command other than a COMMAND INHIBIT or NOP.
5. Starting at some point during this 100
μs period, bring CKE HIGH. Continuing at least through the end of this period, one or more
COMMAND INHIBIT or NOP commands must be applied.
6. Perform a PRECHARGE ALL command.
7. Wait at least tRP time; during this time, NOPs or DESELECT commands must be given. All banks will complete their precharge,
thereby placing the device in the all banks idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode register will power up in an unknown state, it
should be loaded with desired bit values prior to applying any operational command. Using the LMR command, program the mode
register. The mode register is programmed via the MODE REGISTER SET command with BA1 = 0, BA0 = 0 and retains the stored
information until it is programmed again or the device loses power. Not programming the mode register upon initialization will result
in default settings which may not be desired. Outputs are guaranteed High-Z after the LMR command is issued. Outputs should be
High-Z already before the LMR command is issued.
13. Wait at least tMRD time, during which only NOP or DESELECT commands are allowed.
At this point, the DRAM is ready for any valid command.
Note: If desired, more than two AUTO REFRESH commands can be issued in the sequence. After steps 9 and 10 are complete, repeat
them until the desired number of AUTO REFRESCH + tRFC loops is achieved.
REGISTER DEFINITION
Mode Register
The mode register is used to set a specific mode of operation for the SDRAM. These definitions include Burst length (BL), the CAS
latency (CL), and the write burst mode as shown in Figure 4. The mode register is programmed using the LOAD MODE REGISTER
command and retains the stored setting information until either reprogrammed or device power is lost. Mode register bits M0-M2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5962F0253401VXC | 2.5 V FIXED POSITIVE REGULATOR, CDFP16 |
| L491333DIE2V | 3.3 V FIXED POSITIVE REGULATOR, UUC |
| 5962F9654403QXA | OTHER DECODER/DRIVER, CDFP16 |
| 5962F9657601QCX | AC SERIES, 4-BIT LOOK-AHEAD CARRY GENERATOR, TRUE OUTPUT, CDIP16 |
| 5962F9657701VXC | ACT SERIES, 4-BIT LOOK-AHEAD CARRY GENERATOR, TRUE OUTPUT, CDFP16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962D9563201VXC | 制造商:STMicroelectronics 功能描述:RS-432LINE DRIVERQUADFLAT16, GOLD - Bulk |
| 5962D9666301VXC | 制造商:STMicroelectronics 功能描述:RS-432LINE DRIVERQUADFLAT16, GOLD - Bulk |
| 5962F0052301QXC | 制造商:Intersil Corporation 功能描述: |
| 5962F0052301VXC | 制造商:Intersil Corporation 功能描述: |
| 5962F0151001VXC | 制造商:Intersil Corporation 功能描述:RAD SEU HARD QUAD COMPARATOR, CLASS V - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。