參數(shù)資料
型號(hào)： 5962D1022901QXC
元件分類(lèi)： DRAM
英文描述： 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128
封裝： CERAMIC, QFP-128
文件頁(yè)數(shù)： 14/68頁(yè)
文件大?。?/td> 1475K
代理商： 5962D1022901QXC
21
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will
continue until terminated (at the end of the page, it wraps to the start address and continue). Data from any READ burst may be
truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from
a READ command.
In either case, a continuous flow of data can be maintained. The first data element from the new burst either follows the last element
of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be
issued x cycles before the clock edge at which the last desired data element is valid where x = CL - 1. This is shown in Figure 9 for
CL = 2 and CL = 3; data element n + 3 is either the last of a burst of four or the last desired of a longer burst.
The SDRAM uses a pipelined architecture and, therefore, does not require the 2n rule associated with a pre-fetch architecture. A
READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can
be performed to the same bank, as shown in Figure 11, or each subsequent READ may be performed to a different bank.
Figure 9: CAS Latency
READ
NOP
Data
T3
T2
T1
T0
tOH
tAC
tLZ
CL = 2
CLK
Command
DQ
READ
NOP
Data
T3
T2
T1
T0
tOH
tAC
tLZ
CL = 3
CLK
DQ
NOP
Command
Don’t Care
Undefined
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