參數(shù)資料
型號(hào)： 5962D1022901QXC
元件分類： DRAM
英文描述： 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128
封裝： CERAMIC, QFP-128
文件頁(yè)數(shù)： 28/68頁(yè)
文件大?。?/td> 1475K
代理商： 5962D1022901QXC
34
Burst READ/Single WRITE
The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this
mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of opera-
tion (M9 = 0).
Concurrent Auto Precharge
An access command to (READ or WRITE) another bank, while an access command with auto precharge enabled is executing is not
allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
READ with Auto Precharge
Interrupted by a READ (with or without auto precharge): A READ to bank m interrupts a READ on bank n, CL later. The
PRECHARGE to bank n begins when the READ to bank m is registered (see Figure 28).
Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m interrupts a READ on bank n when registered. DQM
should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will
begins when the WRITE to bank m is registered (see Figure 29).
Figure 27: READ with Auto Precharge Interrupted by a READ
NOP
READ AP
NOP
Page Active
Read with burst of 4
Interrupt Burst, Precharge
Idle
Page Active
Read with burst of 4
Precharge
BANK n
Dout a
Dout a+1
Dout d
Dout d+1
CL = 3 (Bank m)
CL = 3 (Bank n)
tRP BANK n
Notes:
1. DQM is LOW.
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANKn
BANKm
ADDRESS
DQ(CL=3)
Don’t Care
Transitioning Data
Internal States
BANK n
COL a
READ AP
BANK m
COL d
tRP BANK m
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