參數(shù)資料
型號(hào): 5962D1022901QXC
元件分類: DRAM
英文描述: 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128
封裝: CERAMIC, QFP-128
文件頁(yè)數(shù): 5/68頁(yè)
文件大?。?/td> 1475K
代理商: 5962D1022901QXC
13
Notes:
1. Program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices.
M9
Write Burst Mode
0
Programmed burst length
1
Single location access
Figure 4: Mode Register Definition
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved1
WB
Op Mode
CAS Latency
BT
Burst Length
M6
M5
M4
CAS Latency
0
Reserved
0
1
Reserved
0
1
0
2
0
1
3
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Reserved
M8
Burst Type
0
Sequential
1
Interleaved
M2 M1 M0
Burst Length
M3 = 0
M3 = 1
0
1
0
1
2
0
1
0
4
0
1
8
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Full Page
Reserved
M8
M7
M6-M0
Operating Mode
0
Defined
Standard Operation
-
All other states reserved
Address Bus
Mode Register (Mx)
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