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參數(shù)資料
| 型號： | 5962D1022901QXC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 4/68頁 |
| 文件大?。?/td> | 1475K |
| 代理商： | 5962D1022901QXC |
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12
specifies the BL, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CL, M7 and M8 specifies the operation
mode, M9 specifies the write burst mode, M10 and M11 are reserved. Address M12 is undefined, but should be driven low during
mode register programming. All references to bit(s) Mx in this document affect the mode register.
Burst Length (BL)
All read and write activity to the SDRAMs are burst oriented. The burst mode is selected by programming BL as described above.
Burst length of 1, 2, 4, and 8 locations are available for both sequential and interleaved burst types. A full page burst is also available
in sequential mode only and is used in conjunction with BURST TERMINATE command to generate arbitrary burst lengths. Re-
served states for BL should not be used as they may result in undefined operations.
Whenever a read or write command is issued a block of columns is selected that is equal to the BL. All access for that burst takes
place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-
A9, and A11when BL = 2, A2-A9, and A11when BL = 4, A3-A9, and A11when BL = 8. The remaining least significant address bits
are used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved: this is referred to as the burst type and is
selected via bit M3.
The ordering of the accesses with the burst is determined by BL1, the burst type and the staring column address, as shown in Table 3.
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