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參數(shù)資料
| 型號： | 5962D1022901QXC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 26/68頁 |
| 文件大小： | 1475K |
| 代理商： | 5962D1022901QXC |
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32
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress.
If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and
output buffers, excluding CKE, for maximumpower savings while in standby. The device may not remain in the power-down state
longer than the refresh period (32ms) since no refresh operations are performed in this mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting
tCKS). See Figure 24.
Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode,
the internal clock is deactivated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or
data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains
driven. Burst counters are not incremented, as long as the clock is suspended (see examples in Figures 25 and 26).
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation resumes on the subsequent
positive clock edge. The device may not remain in clock suspend state longer than the refresh period (32ms) since no refresh
operations are performed in this mode.
Figure 24: POWER-DOWN
NOP
ACTIVE
Input Buffers Gated Off
tCKS
All Banks Idle
Enter Power-Down Mode
Exit Power-Down Mode
CLK
CKE
Command
Don’t Care
tCKS
tRCD
tRAS
tRC
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