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參數(shù)資料
| 型號： | 5962D1022901QXC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 30/68頁 |
| 文件大?。?/td> | 1475K |
| 代理商： | 5962D1022901QXC |
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36
Data for any WRITE burst may be truncated with a subsequent READ comment, and data for a fixed-length WRITE burst may be
immediately followed by a READ command. After the READ command is registered, the data inputs will be ignored, and WRITEs
will not be executed. An example is shown. Data n+1 is either the last of a burst of two or the latest desired of a longer burst.
WRITE with Auto Precharge
Interrupted by a READ (with or without auto precharge): A READ to bank m interrupts a WRITE on bank n when registered,
with the data-out appearing CL later. The PRECHARGE to bank n begins after tWR is met, where tWR begins when the
READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to
bank m (see Figure 29).
Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m interrupts a WRITE on bank n when registered.
The PRECHARGE to bank n begins after tWR is met, where tWR begins when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (see Figure 30).
Figure 29: WRITE with Auto Precharge Interrupted by a READ
NOP
WRITE AP
NOP
Page Active
Read with burst of 4
Interrupt Burst, write-back
Precharge
Page Active
Read with burst of 4
bank n col a
bank m cl d
Din a
a+1
Dout d
d+1
tWR BANK n
Notes:
1. DQM is Low.
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANKn
BANKm
ADDRESS
DQ(CL=3)
BANK n
READ AP
BANK m
Internal States
tRP BANK n
tWR BANK m
Don’t Care
Transitioning Data
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