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參數資料
| 型號： | 5962D1022901QXC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數： | 19/68頁 |
| 文件大?。?/td> | 1475K |
| 代理商： | 5962D1022901QXC |
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26
WRITES
WRITE bursts are initiated with a WRITE command, as shown in Figure 16.
The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled
for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data
elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQs remains High-Z and any additional input data will be ignored (see Figure 17 on page 26). A
full-page burst will continue until terminated (at the end of the page, it will wrap to the start address and continue). Data for any
WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately
followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE
command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 18.
Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined architecture
and, therefore, does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank,
as shown in Figure 19, or each subsequent WRITE may be performed to a different bank.
Figure 16: Write Command
Don’t Care
Column Address
Bank Address
T0
Enable Auto Precharge
Disable Auto Precharge
CLK
CKE
CS#
RAS#
CAS#
WE#
A[0-9], A11
A10
BA(0,1)
A12
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