參數(shù)資料
型號: 5962D1022901QXC
元件分類: DRAM
英文描述: 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128
封裝: CERAMIC, QFP-128
文件頁數(shù): 42/68頁
文件大?。?/td> 1475K
代理商: 5962D1022901QXC
47
TIMING DIAGRAMS
Figure 31: Initialize and Load Mode Register
NOP
PRE
NOP
LOAD
NOP
ACTIVE
CODE
ROW
CODE
ROW
ALL BANKS
BANK
tAH
tAS
tAH
tAS
tCMH
tCMS
tCKH
tCKS
tMRD
tRFC
tCL
tCH
tRP
tCK
Notes:
1.
The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
2.
If CS is HIGH at clock HIGH time, all commands applied are NOP.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at Tp+1.
ALL BANKS
SINGLE BANK
High-Z
T0
T1
Tn + 1
CLK
CKE
COMMAND
DQM
A(0:9,11:12)
A(10)
BA(0,1)
DQ
To +1
Tp + 1
Tp + 2
Tp + 3
Don’t Care
CHARGE
MODE
REGISTER
NOP
AUTO
REFRESH
AUTO
REFRESH
Power-up:
Vdd and
CLK stable
Precharge
all banks
AUTO REFRESH
Program mode register 2, 3, 4
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