參數(shù)資料
型號(hào)： XRT72L74
廠商： Exar Corporation
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 83/104頁(yè)
文件大?。?/td> 1301K
代理商： XRT72L74
á
XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.0
83
T
ABLE
80:
R
X
CP I
NTERRUPT
S
TATUS
R
EGISTER
R
EGISTER
79 R
X
CP I
NTERRUPT
S
TATUS
R
EGISTER
H
EX
A
DDRESS
: 0
X
4F
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
OAM Buffer/FIFO Overflow
RUR
0
0: Receive OAM Cell Buffer/FIFO has not experienced an “Overrun” event
since the last read of this register.
1: Receive OAM Cell Buffer/FIFO has experienced an “Overrun” event since
the last read of this register.
N
OTE
:
This bit-field is only active if the XRT72L74 is operating in the “ATM
UNI” Mode.
6-3
Unused
RO
0
2
OAM Interrupt Status/
OAM Cell Pending
RUR/RO
0
OAM FIFO mode:
0: Indicates that the “Receive OAM Cell FIFO” is empty and does not con-
tain any new OAM cell data.
1: Indicates that there at least one unread OAM cell exists within the
“Receive OAM Cell FIFO”.
N
OTE
:
If the “Receive OAM Cell” Buffer/FIFO is configured to operate in the
“FIFO” Mode, then this bit-field is “Read-Only”.
OAM Buffer Mode
:
0: Indicates that the “Receipt of OAM Cell” Interrupt has NOT occurred since
the last read of this register.
1: Indicates that the “Receipt of OAM Cell” Interrupt has occurred since the
last read of this register.
1
LCD Interrupt Status
RUR
0
0: Indicates that the “Change in LCD Condition” interrupt has NOT occurred
since the last read of this register.
1: Indicates that the “Change in LCD Condition” Interrupt has occurred since
the last read of this register.
N
OTE
:
This bit-field is only active if the XRT72L74 is operating in the “ATM
UNI” Mode.
0
HEC Byte Error Interrupt
Status
RUR
0
0: Indicates that the “Detection of HEC Byte” Error has NOT occurred since
the last read of this register.
1: Indicates that the “Detection of HEC Byte” Error has occurred since the
last read of this register.
N
OTE
:
This bit-field is only active if the XRT72L74 is operating in the “ATM
UNI” Mode.
T
ABLE
81:
R
X
CP I
DLE
C
ELL
P
ATTERN
H
EADER
B
YTE
-1
R
EGISTER
80 R
X
CP I
DLE
C
ELL
P
ATTERN
H
EADER
B
YTE
-1 H
EX
A
DDRESS
: 0
X
50
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
Rx Idle Cell Pattern 1
R/W
0x00
This register (along with the “Rx Idle Cell Mask 1” register) permits the user
to specify the “Idle Cell Filtering” criteria for Header Byte 1.
N
OTES
:
1. This register should be set to “0x00” when the Receive Cell Proces-
sor is receiving “ATM Forum” standard Idle Cells.
2. This bit-field is only active if the XRT72L74 is operating in the “ATM
UNI” Mode.
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