參數(shù)資料
型號: XRT72L74
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 35/104頁
文件大?。?/td> 1301K
代理商: XRT72L74
á
XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.0
35
t
8
TxUSoC Hold Time from rising edge
of TxUClk
1
ns
t
9
TxUAddr[4:0] Setup Time to rising
edge of TxUClk
4
ns
t
10
TxUAddr[4:0] Hold Time from rising
edge of TxUClk
1
ns
t
11
TxUClav signal valid (not Hi-Z) from
first TxUClk rising edge of valid and
correct TxUAddr[4:0]
6
16
ns
t
12
TxUClav signal Hi-Z from first TxUClk
rising edge of different TxUAddr[4:0]
9
19
ns
Transmit Cell Processor (GFC Serial Input Port)—See Figure 5
t
13
Clock Period of TxGFCClk
232
ns
There will be a periodic clock
gap every six clocks.
fTxGFCClk
Frequency of TxGFCClk
5.592
MHz
t
14
Delay from rising edge of TxGFCClk
to rising edge of TxGFCMSB pin
1.43
ns
t
15
Pulse width of TxGFCMSB signal
232
ns
t
16
TxGFC Data Setup time to rising edge
of TxGFCClk
7
ns
t
17
TxGFC Data Hold time from rising
edge of TxGFCClk
3
ns
Transmit PLCP Processor (Serial Input Port)—See Figure 6
t
18
Clock Period of TxPOHClk signal
232
ns
periodically gapped
t
19
Delay from rising edge of
TxPOHFrame signal to rising edge of
TxPOHClk signal
90
113
ns
>0.5 t
18
t
20
TxPOH setup time to rising edge of
TxPOHClk signal
11
ns
t
21
TxPOH signal hold time from rising
edge of TxPOHClk signal
3
ns
t
22
TxPOHIns signal setup time to rising
edge of TxPOHClk
11
ns
t
23
TxPOHIns signal hold time from rising
edge of TxPOHClk
3
ns
Transmit DS3 Framer (Serial Input Port)—See Figure 7
fTxOHClk
Frequency of TxOHClk signal
526.3
kHz
t
24
Period of TxOHClk clock signal
1900
ns
44.736MHz/85
t
25
Delay from rising edge of TxOHFrame
signal to rising edge of TxOHClk signal
950
970
ns
>0.5 t
24
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Test Conditions: T
A
= 25°C, VDD = 3.3V ± 5% unless otherwise specified
S
YMBOL
P
ARAMETER
M
IN
.
T
YP
.
M
AX
.
U
NITS
C
ONDITIONS
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