參數(shù)資料
型號: XRT72L74
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 38/104頁
文件大小: 1301K
代理商: XRT72L74
XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
REV. P1.0.0
á
PRELIMINARY
38
t
62
RxUClav signal valid (not Hi-Z) from
first RxUClk rising edge of valid and
correct TxUAddr[4:0]
1
7.8
16
ns
t
63
RxUClav signal Hi-Z from first RxUClk
rising edge of different RxUAddr[4:0].
1
9.2
16
ns
Microprocessor Interface—Intel -- See Figure 16 and Figure 17
t
64
A8—A0 Setup Time to ALE_AS Low
3
ns
t
65
A8—A0 Hold Time from ALE_AS Low.
2
ns
t
66
RD_DS, WR_RW Pulse Width
30
ns
Intel Type Read Operations -- See Figure 16
t
67
Data Valid from RD_DS Low.
6
11
ns
t
68
Data Bus Floating from RD_DS High.
10
ns
t
69
ALE to RD Time
4
ns
t
70
RD Time to :”NOT READY” (e.g.,
RDY_DTCK toggling “Low”)
15
23
ns
Intel Type Write Operations -- See Figure 17
t
71
Data Setup Time to WR_RW High
4
ns
t
72
Data Hold Time from WR_RW High
2
ns
t
73
High Time between Reads and/or
Writes
20
ns
t
74
ALE to WR Time
4
ns
t
770
CS Assertion to falling edge of
WR_RW
20
ns
Microprocessor Interface—Motorola Read Operations -- See Figure 18
t
78
A8—A0 Setup Time to falling edge of
ALE_AS
5
ns
t
79
A8—A0 Rising edge of RD_DS to rising
edge of RDY_DTCK
0
ns
t
80
Rising edge of RDY_DTCK to tri-state
of D[7:0]
0
ns
Microprocessor Interface—Write Operations -- See Figure 19
t
78
A8—A0 Setup Time to falling edge of
ALE_AS
5
ns
t
81
D[7:0] Setup Time to falling edge of
RD_DS
10
ns
t
82
Rising edge of RD_DS to rising edge of
RDY_DTCK delay
0
ns
Reset Pulse Width—Both Motorola and Intel Operations -- See Figure 20
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Test Conditions: T
A
= 25°C, VDD = 3.3V ± 5% unless otherwise specified
S
YMBOL
P
ARAMETER
M
IN
.
T
YP
.
M
AX
.
U
NITS
C
ONDITIONS
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