參數(shù)資料
型號(hào)： XRT72L74
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 4/104頁
文件大?。?/td> 1301K
代理商： XRT72L74
XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
REV. P1.0.0
á
PRELIMINARY
4
The Receive Cell Processor block will also verify
the CRC-10 value within all received OAM cells, per
ITU-T I.610.
Detects and generates interrupts upon “Detection
of HEC Byte errors”, “Change in LCD (Loss of Cell
Delineation) condition” and “Receipt of OAM Cell”.
The Receive UTOPIA Interface Block
Provides a “UTOPIA Level -2” compliant interface to
either the ATM or the ATM Adaptation Layer.
Can be configured to operate in either the “Single-
PHY” or “Multi-PHY” Modes.
Supports either “Cell-Level” or “Octet-Level” Hand-
shaking.
Receive UTOPIA Data Bus can be configured to be
either 8 or 16-bits wide.
The RxFIFO, within the Receive UTOPIA Interface
block will temporarily hold any ATM cells that pass
through the Receive Cell Processor, where they can
be read out by the ATM Layer processor, over the
Receive UTOPIA Data Bus.
The size of the “RxFIFO” is 16 cells.
Supports read operations (from the ATM Layer
device) at rates upto 50MHz.
Detects and generates interrupts upon “Detection
of RUNT cells” and “Overrun of RxFIFO”.
THE TRANSMIT SECTION
The purpose of the Transmit section of the XRT72L74
DS3 ATM UNI is to allow a local ATM Layer (or ATM
Adaptation Layer) processor to transmit ATM Cell da-
ta to a remote piece of equipment via a public or
leased DS3 transport medium.
The Transmit Section of the XRT72L74 DS3 UNI con-
sists of the following functional blocks.
Transmit UTOPIA Interface Block
Transmit Cell Processor Block
Transmit PLCP Processor Block
Transmit DS3 Framer Block
Each of these functional blocks, within the Transmit
Section (of the UNI/Framer) will do the following:
Transmit UTOPIA Interface Block
Can be configured to operate in either the “Single-
PHY” or Multi-PHY” Mode.
Supports either the “Cell-Level” or “Octet-Level”
Handshaking Mode.
Transmit UTOPIA Data Bus can be configured to be
either 8 or 16-bits wide.
Allow the ATM Layer processor to write ATM cells
into the Transmit FIFO (within the Transmit UTOPIA
Interface block) via a standard UTOPIA Level 2
interface.
The size of the “TxFIFO” is 16 cells. However, the
operating depth can be configured to be 4, 8, 12 or
16 cells.
Supports write operations (from the ATM Layer
device) at rates upto 50MHz.
Detects and generates interrupts upon “Detection
of Parity Errors”, “Detection of RUNT cells” and
“Overrun of TxFIFO”.
Transmit Cell Processor Block
The Transmit Cell Processor will read in ATM cells
from the Transmit FIFO (if available) for further
processing.
If no cell is available within the Transmit FIFO, then
the Transmit Cell Processor will automatically gen-
erate an Idle cell. The UNI is equipped with on-chip
registers to allow for the generation of customized
Idle cells.
The UNI provides 54 bytes of on-chip RAM that
allows for the generation and transmission of “user-
specified” OAM cells. The Transmit Cell Processor
will generate and transmit these OAM cells upon
software command.
The Transmit Cell Processor block will also com-
pute and insert a CRC-10 value into each “out-
bound” OAM cell, per ITU-T I.610.
The Transmit Cell Processor will (optionally) scramble
the Cell Payload bytes and (optionally) compute
and insert the HEC (Header Error Check) byte. This
HEC byte will be inserted into the fifth octet of each
cell prior to being transferred to the Transmit PLCP
Processor (or the Transmit DS3 Framer).
Transmit PLCP Processor Block
The Transmit PLCP Processor will pack 12 ATM cells
into each PLCP frame and automatically determine
the nibble-stuffing option of the current PLCP frame.
These PLCP frames will also include an overhead
byte that reflect BIP-8 (Bit Interleaved Parity) calcula-
tion results, a byte that reflects the current stuffing
option status of the current PLCP frame, Path Over-
head and Identifier bytes, and diagnostic-related
bytes reflecting any detected BIP-8 errors and
alarm conditions detected in the Receive section of
the UNI chip.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT72L74IB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
XRT7300 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7300ES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT7300IV 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI . . RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT7300IV-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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