XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
REV. P1.0.0
á
PRELIMINARY
72
T
ABLE
50:
PMON M
ULTIPLE
-
BIT
HEC E
RROR
C
OUNT
- LSB
R
EGISTER
49 PMON M
ULTIPLE
-
BIT
HEC E
RROR
C
OUNT
- LSB H
EX
A
DDRESS
: 0
X
31
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
M-HEC Error Count Low-
byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON Multiple-Bit HEC Error
Count Register - MSB” contains the 16 bit value for the total number of Multi-
bit HEC byte errors that have been detected since the last read of this regis-
ter. This register contains the “Low” byte value of this 16-bit expression.
N
OTE
:
This register is only active if the device has been configured to oper-
ate in the “ATM UNI” Mode.
T
ABLE
51:
PMON R
ECEIVED
I
DLE
C
ELL
C
OUNT
/PRBS E
RROR
C
OUNT
- MSB
R
EGISTER
50 PMON R
ECEIVED
I
DLE
C
ELL
C
OUNT
/PRBS E
RROR
C
OUNT
- MSB H
EX
A
DDRESS
: 0
X
32
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
Rx Idle Cell Count High-
byte/
PRBS Error Count High-
byte
RUR
0x00
ATM Mode
: This register, along with “PMON Received Idle Cell
Count - LSB” contains the 16 bit value for the total number of idle
cells that have been received by the Receive Cell Processor, since
the last read of this register. This register contains the “High” byte
value of this 16-bit expression.
Clear Channel Framer Mode
: This register, along with “PMON
PRBS Error Count - LSB” regster contains the 16 bit value for the
total number of PRBS bit errors that have been received (by the
PRBS Receiver) since the last read of this register. This register
contains the “High” byte value of this 16-bit expression.
T
ABLE
52:
PMON R
ECEIVED
I
DLE
C
ELL
C
OUNT
/PRBS E
RROR
C
OUNT
- LSB
R
EGISTER
51 PMON R
ECEIVED
I
DLE
C
ELL
C
OUNT
/PRBS E
RROR
C
OUNT
- LSB H
EX
A
DDRESS
: 0
X
33
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
Rx Idle Cell Count Low-
byte/
PRBS Error Count Low-
byte
RUR
0x00
ATM Mode
: This register, along with “PMON Received Idle Cell
Count - MSB” contains the 16 bit value for the total number of idle
cells that have been received by the Receive Cell Processor, since
the last read of this register. This register contains the “Low” byte
value of this 16-bit expression.
Clear Channel Framer Mode:
This register, along with “PMON
PRBS Error Count - MSB” regster contains the 16 bit value for the
total number of PRBS bit errors that have been received (by the
PRBS Receiver) since the last read of this register. This register
contains the “Low” byte value of this 16-bit expression.