參數(shù)資料
型號(hào)： XRT72L74
廠(chǎng)商： Exar Corporation
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 69/104頁(yè)
文件大?。?/td> 1301K
代理商： XRT72L74
á
XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.0
69
T
ABLE
38:
PMON P-B
IT
E
RROR
C
OUNT
R
EGISTER
- LSB
R
EGISTER
37 PMON P-B
IT
E
RROR
C
OUNT
R
EGISTER
- LSB H
EX
A
DDRESS
: 0
X
25
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
P-Bit Error Count Low-byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON P-Bit Error Count Reg-
ister - MSB” contains the 16 bit value for the total number of P Bit errors that
have been detected since the last read of this register. This register con-
tains the “Low” byte value of this 16-bit expression.
T
ABLE
39:
PMON FEBE E
VENT
C
OUNT
R
EGISTER
- MSB
R
EGISTER
38 PMON FEBE E
VENT
C
OUNT
R
EGISTER
- MSB H
EX
A
DDRESS
: 0
X
26
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
FEBE Event Count High-
byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON FEBE Event Count
Register - LSB” contains the 16 bit value for the total number of FEBE events
that have been detected since the last read of this register. This register
contains the “High” byte value of this 16-bit expression.
N
OTE
:
This register is only active if the XRT72L74 has been configured to
support the “C-bit Parity” Framing format.
T
ABLE
40:
PMON FEBE E
VENT
C
OUNT
R
EGISTER
- LSB
R
EGISTER
39 PMON FEBE E
VENT
C
OUNT
R
EGISTER
- LSB H
EX
A
DDRESS
: 0
X
27
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
FEBE Event Count Low-
byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON FEBE Event Count
Register - MSB” contains the 16 bit value for the total number of FEBE
events that have been detected since the last read of this register. This reg-
ister contains the “Low” byte value of this 16-bit expression.
N
OTE
:
This register is only active if the XRT72L74 has been configured to
support the “C-bit Parity” Framing format.
T
ABLE
41:
PMON PLCP BIP-8 E
RROR
C
OUNT
R
EGISTER
- MSB
R
EGISTER
40 PMON PLCP BIP-8 E
RROR
C
OUNT
R
EGISTER
- MSB H
EX
A
DDRESS
: 0
X
28
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
PLCP BIP Error Count
High-byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON PLCP BIP-8 Error
Count Register - LSB” contains the 16 bit value for the total number of PLCP
BIP-8 Errors that have been detected since the last read of this register. This
register contains the “High” bye value of this 16-bit expression.
N
OTE
:
This register is only active if the XRT72L74 has been configured to
operate in both the “ATM UNI” and “PLCP” Modes.
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