á
XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.0
63
T
ABLE
24:
T
X
DS3 M-B
IT
M
ASK
R
EGISTER
R
EGISTER
23 T
X
DS3 M-B
IT
M
ASK
R
EGISTER
H
EX
A
DDRESS
: 0
X
17
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Tx FEBE Dat(2)
R/W
0
The Transmit DS3 Framer block will transmit the value “TxFEBEDat[2:0]”
within the “FEBE” bit-fields, if the “FEBE Register Enable” bit-field is set to
“1”.
N
OTE
:
This bit-field is only active if the XRT72L74 is configured to support
the “C-bit Parity” Framing Format.
6
Tx FEBE Dat(1)
R/W
0
5
Tx FEBE Dat(0)
R/W
0
4
FEBE Register Enable
R/W
0
0: FEBE bits, for transmission, are internally generated based on conditions,
as detected by the Receive DS3 Framer block.
1: Transmit FEBE bits are taken from the TxFEBEDat [2:0] register bits
N
OTE
:
This bit-field is only active if the XRT72L74 is configured to support
the “C-bit Parity” Framing Format.
3
Mbit Mask(2)
R/W
0
The Transmit DS3 Framer block performs an XOR operation of the MBitMask
bits with the corresponding “M” bit, within each outbound DS3 frame.
MBitMask(2) corresponds to first M-Bit (M0) in DS3 frame,
MBitMask(1) corresponds to second M-Bit (M1) in DS3 frame,
MBitMask(0) corresponds to last M-Bit (M0) in DS3 frame
N
OTES
:
1. Setting any of these bit-fields to “1”, will cause an “erred” M-bit to be
transmitted onto the line.
2. For normal operation, the user should set each of these bit-fields to
“0”.
2
Mbit Mask(1)
R/W
0
1
Mbit Mask(0)
R/W
0
0
TxError PBit
R/W
0
0: P Bits are calculated from input payload and inserted into the P-bit fields.
1: Calculated P Bits are inverted before transmission (thereby creating a “P-
Bit” Error).
N
OTE
:
For normal operation, set this bit-field to “0”.
T
ABLE
25:
T
X
DS3 F-B
IT
M
ASK
1 R
EGISTER
R
EGISTER
24 T
X
DS3 F-B
IT
M
ASK
1 R
EGISTER
H
EX
A
DDRESS
: 0
X
18
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-4
Unused
RO
0
3
F-bit Mask (27)
R/W
0
The Transmit DS3 Framer block performs an XOR operation of the F-Bit
Mask bits, with the corresponding “F” bits, within each outbound DS3 frame.
FBitMask(0) corresponds to first F-Bit (F1) is the DS3 frame, FBitMask (1)
corresponds to 2nd F-Bit (F0)in the DS3 frame,...FBitMask(27) corresponds
to the last F-Bit of the M-Frame.
N
OTES
:
1. Setting any of these bit-fields to “1” will cause an “erred” F-bit to be
transmitted onto the line.
2. For normal operation, the user should set each of these bit-fields to
“0”.
2
F-bit Mask (26)
R/W
0
1
F-bit Mask (25)
R/W
0
0
F-bit Mask (24)
R/W
0