XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
REV. P1.0.0
á
PRELIMINARY
54
T
ABLE
8:
T
EST
C
ELL
E
RROR
A
CCUMULATOR
H
OLDING
R
EGISTER
R
EGISTER
7 T
EST
C
ELL
E
RROR
A
CCUMULATOR
H
OLDING
R
EGISTER
H
EX
A
DDRESS
: 0
X
07
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
TEST CELL HOLDING
REGISTER
RO
0x00
Holds the “Unread” byte of the 16-bit Test Cell Error Accumulator, when that
register is read. The XRT72L74 will transfer the contents of the “Unread”
byte to this “Holding” register, anytime the Bidirectional Data Bus (of the
Microprocessor Interface) is configured to be 8-bits wide.
N
OTE
:
This register is only active if the XRT72L74 has been configured to
operate in the “ATM UNI” Mode.
T
ABLE
9:
T
EST
C
ELL
H
EADER
B
YTE
-1
R
EGISTER
8 T
EST
C
ELL
H
EADER
B
YTE
-1 H
EX
A
DDRESS
: 0
X
08
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
TEST CELL HEADER
BYTE 1
R/W
0x11
Test Cell Header Byte - 1
Permits the user to define the value of “Header Byte # 1” within each Test Cell
which is generated by the “Test Cell Generator”.
N
OTE
:
This register is only active if the XRT72L74 has been configured to
operate in the “ATM UNI” Mode.
T
ABLE
10:
T
EST
C
ELL
H
EADER
B
YTE
-2
R
EGISTER
9 T
EST
C
ELL
H
EADER
B
YTE
-2 H
EX
A
DDRESS
: 0
X
09
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
TEST CELL HEADER
BYTE 2
R/W
0x22
Test Cell Header Byte - 2
Permits the user to define the value of “Header Byte # 2” within each Test Cell
which is generated by the “Test Cell Generator”.
N
OTE
:
This register is only active if the XRT72L74 has been configured to
operate in the “ATM UNI” Mode.
T
ABLE
11:
T
EST
C
ELL
H
EADER
B
YTE
-3
R
EGISTER
10 T
EST
C
ELL
H
EADER
B
YTE
-3 H
EX
A
DDRESS
: 0
X
0A
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
TEST CELL HEADER
BYTE 3
R/W
0x33
Test Cell Header Byte - 3
Permits the user to define the value of “Header Byte # 3” within each Test Cell
which is generated by the “Test Cell Generator”.
N
OTE
:
This register is only active if the XRT72L74 has been configured to
operate in the “ATM UNI” Mode.
T
ABLE
12:
T
EST
C
ELL
H
EADER
B
YTE
-4
R
EGISTER
11 T
EST
C
ELL
H
EADER
B
YTE
-4 H
EX
A
DDRESS
: 0
X
0B
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
TEST CELL HEADER
BYTE 4
R/W
0x44
Test Cell Header Byte - 4
Permits the user to define the value of “Header Byte # 4” within each Test Cell
which is generated by the “Test Cell Generator”.
N
OTE
:
This register is only active if the XRT72L74 has been configured to
operate in the “ATM UNI” Mode.