參數(shù)資料
型號(hào): XRT72L74
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 22/104頁
文件大?。?/td> 1301K
代理商: XRT72L74
XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
REV. P1.0.0
á
PRELIMINARY
22
D3
D2
E3
E2
TxOHFrame_0
TxOHFrame_1
TxOHFrame_2
TxOHFrame_3
O
Transmit Overhead Framing Pulse:
The function of this pin is same in both Clear Channel and ATM UNI modes of
XRT72L74. When the external interface samples this pin "High" at the rising edge
of TxOHClk, it should provide 'X' bit (first OH bit within DS3 frame) on the TxOH
pin. This signal is "High" for one TxOHClk duration and repeats once for each DS3
frame.
A3
A1
B2
C1
TxOHIns_0
TxOHIns_1
TxOHIns_2
TxOHIns_3
I
Transmit Overhead Data Insert Input:
The function of this pin is the same in both Clear Channel and ATM UNI Modes of
the XRT72L74. This pin is used to indicate if the OH bit should be taken from the
external interface. The OH data on TxOH will be considered by the only if this pin
is "High" during OH positions.
B1
C6
C16
D22
TxPOS_0
TxPOS_1
TxPOS_2
TxPOS_3
O
Transmit Positive Polarity Pulse:
The exact role of this output pin depends upon whether the UNI is operating in the
Unipolar or Bipolar Mode.
Unipolar Mode:
This output pin functions as the “Single-Rail” output signal for the “outbound” DS3
data stream. The signal, at this output pin, will be updated on the “user-selected”
edge of the TxLineClk signal.
Bipolar Mode:
This output pin functions as one of the two dual rail output signals that commands
the sequence of pulses to be driven on the line. TxNEG is the other output pin.
This input is typically connected to the TPDATA input of the external DS3 Line
Interface Unit IC. When this output is asserted, it will command the LIU to generate
a positive polarity pulse on the line.
Rx DS3 Framer
F26
E24
E25
E26
RxAIS_0
RxAIS_1
RxAIS_2
RxAIS_3
O
Receive “Alarm Indication Signal” Output pin:
The UNI/Framer IC will assert this pin to indicate that the Alarm Indication Signal
(AIS) has been identified in the Receive DS3 data stream. An “AIS” is detected if
the payload consists of the recurring pattern of 1010... and this pattern persists for
63 M-frames. An additional requirement for AIS indication is that the C-bits are set
to 0, and the X-bits are set to 1. This pin will be negated when a sufficient number of
frames, not exhibiting the “1010...” pattern in the payload has been detected.
B18
A18
B17
A17
RxFrame_0
RxFrame_1
RxFrame_2
RxFrame_3
O
Receive Boundary of DS3 Frame Output Indicator:
The exact functionality of this output pin depends upon whether the XRT72L74
UNI/Framer IC is operating in the Clear Channel or ATM UNI Mode.
Clear Channel Mode:
In clear channel mode this pin is pulsed “High” for one DS3 clock period whenever
the 'X' bit (first OH bit in the DS3 frame) of the frame is being output on the RxSer
pin. RxSer will contain 'X' bit (first OH bit of DS3 frame) if
this pin is sampled “High”.
ATM UNI Mode:
In the ATM UNI mode, this signal indicates the start of the received DS3 frame and
is "High" for one DS3 clock period.
A2
D11
D18
C25
RxLineClk_0
RxLineClk_1
RxLineClk_2
RxLineClk_3
I
Receive LIU (Recovered) Clock Input:
This input signal serves three purposes:
1. The Receive DS3 Framer uses it to sample and “l(fā)atch” the signals at the RxPOS
and RxNEG input pins (into the Receive DS3 Framer circuitry).
2. This input signal functions as the timing reference for the Receive Framer block.
3. The Transmit DS3 Framer block can be configured to use this input signal as its
timing reference.
N
OTE
:
Note: This signal is the recovered clock from the external DS3 LIU (Line
Interface Unit) IC, which is derived from the incoming DS3 data.
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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