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參數(shù)資料
| 型號： | TSB81BA3I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| 中文描述： | 的IEEE 1394b三端口電纜收發(fā)器/仲裁者 |
| 文件頁數(shù)： | 9/57頁 |
| 文件大小： | 810K |
| 代理商： | TSB81BA3I |
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SLLS559B DECEMBER 2002 REVISED OCTOBER 2003
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
PCLK
TYPE
CMOS
NO.
5
O
PHY clock. Provides a 98.304-MHz clock signal, synchronized with data transfers, to the LLC when the
PHY-link interface is operating in the 1394b mode (BMODE asserted). PCLK output provides a
49.152-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is in
legacy 1394a2000 (BMODE input deasserted).
PD
CMOS
77
I
Power-down input. A high on this terminal turns off all internal circuitry except the cable-active monitor
circuits, which control the CNA output. Asserting the PD input high also activates an internal pulldown
on the RESETz terminal to force a reset of the internal control logic.
PINT
CMOS
1
O
PHY Interrupt. The PHY uses this output to serially transfer status and interrupt information to the link
when PHY-link interface is in the 1394b mode. A bus holder is built into this terminal.
PLLGND
Supply
25,
28
PLL circuit ground terminals. These terminals must be tied together to the low-impedance circuit board
ground plane.
PLLVDD-1.8
Supply
29,
30
PLL 1.8-V circuit power terminals. A combination of high-frequency decoupling capacitors near each
terminal are suggested, such as paralleled 0.1
μ
F and 0.001
μ
F. An additional 1-
μ
F capacitor is
required for voltage regulation, and the PLLVDD-1.8 terminals must be separate from the DVDD-1.8
terminals. These supply terminals are separated from the DVDD-1.8, DVDD-3.3, PLLVDD-3.3 and
AVDD-3.3 terminals internal to the device to provide noise isolation.
PLLVDD-3.3
Supply
31
PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors near the
terminal are suggested, such as paralleled 0.1
μ
F and 0.001
μ
F. Lower frequency 10-
μ
F filtering
capacitors are also recommended. This supply terminal is separated from the DVDD-1.8, DVDD-3.3,
PLLVDD-1.8, and AVDD-3.3 terminals internal to the device to provide noise isolation. The DVDD-3.3
terminals must be tied together at a low-impedance point on the circuit board. The PLLVDD-3.3,
AVDD-3.3, and DVDD-3.3 terminals must be tied together with a low dc impedance connection.
RESETz
CMOS
75
I
Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to VDD
is provided so only an external delay capacitor is required for proper power-up operation (see
power-up
reset
in the APPLICATIONS INFORMATION section). The RESETz terminal also incorporates an
internal pulldown which is activated when the PD input is asserted high. This input is otherwise a
standard logic input, and can also be driven by an open-drain type driver.
RSVD
26
O
This terminal must normally be left unconnected. When this terminal is probed, the terminal will show a
98.304-MHz signal. If this is perceived as an EMI problem, then the terminal may be pulled to ground
through a 10-k
resistor. However, this causes an increase of up to 340
μ
A in device current
consumption.
R0
R1
Bias
23
22
Current setting resistor terminals. These terminals are connected to a precision external resistance to
set the internal operating currents and cable driver output currents. A resistance of 6.34 k
±
1% is
required to meet the IEEE Std 13941995 output voltage limits.
SE
CMOS
35
I
Test control input. This input is used in the manufacturing test of the TSB81BA3. For normal use this
terminal must be pulled low either through a 1-k
resistor to GND or directly to GND.
SM
CMOS
36
I
Test control input. This input is used in the manufacturing test of the TSB81BA3. For normal use this
terminal must be pulled low either through a 1-k
resistor to GND or directly to GND.
TESTM
CMOS
78
I
Test control input. This input is used in the manufacturing test of the TSB81BA3. For normal use this
terminal must be pulled high through a 1-k
resistor to VDD.
Test control input. This input is used in the manufacturing test of the TSB81BA3. For normal use
this terminal must be pulled high through a 1-k
resistor to VDD.
Port 0 twisted-pair differential-signal terminals. Board traces from each pair of positive and
negative differential signal terminals must be kept matched and as short as possible to the external
load resistors and to the cable connector. Please request the S800 1394b layout recommendations
document from your TI representative.
TESTW
CMOS
73
I
TPA0
TPA0+
TPB0
TPB0+
Cable
45,
46,
41,
42
I/O
TPA1
TPA1+
TPB1
TPB1+
Cable
52
53
48
49
I/O
Port 1 twisted-pair differential-signal terminals. Board traces from each pair of positive and
negative differential signal terminals must be kept matched and as short as possible to the external
load resistors and to the cable connector. Please request the S800 1394b layout recommendations
document from your TI representative.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB81BA3IPFP | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3IPFPEP | 功能描述:射頻收發(fā)器 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3PFP | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3PFPG4 | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB82AA2 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394b OHCI-LYNX CONTROLLER |
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