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| 型號： | TSB81BA3I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| 中文描述： | 的IEEE 1394b三端口電纜收發(fā)器/仲裁者 |
| 文件頁數(shù)： | 28/57頁 |
| 文件大小： | 810K |
| 代理商： | TSB81BA3I |
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SLLS559B DECEMBER 2002 REVISED OCTOBER 2003
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394a2000 INTERFACE)
The TSB81BA3 is designed to operate with an LLC such as the Texas Instruments TSB12LV21B, TSB12LV26,
TSB12LV32, TSB42AA4, or TSB12LV01B when the BMODE terminal is tied low. Details of operation for the
Texas Instruments LLC devices are found in the respective LLC data sheets. The following paragraphs describe
the operation of the PHY-LLC interface. This interface is formally defined in IEEE 1394a2000, Section 5A.
The interface to the LLC consists of the PCLK, CTL0CTL1, D0D7, LREQ, LPS, and LKON/DS2 terminals on
the TSB81BA3, as shown in Figure 10.
LKON/DS2
LPS
PCLK (SYSCLK)
LREQ
D0–D7
CTL0–CTL1
Link-Layer
Controller
TSB81BA3
Figure 10. PHY-LLC Interface
The PCLK terminal provides a 49.152-MHz interface system clock. All control and data signals are synchronized
to, and sampled on, the rising edge of PCLK. This terminal serves the same function as the SYSCLK terminal
of 1394a2000 compliant PHY devices.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data
between the TSB81BA3 and LLC.
The D0D7 terminals form a bidirectional data bus, which transfers status information, control information, or
packet data between the devices. The TSB81BA3 supports S100, S200, and S400 data transfers over the
D0D7 data bus. In S100 operation only the D0 and D1 terminals are used; in S200 operation only the D0D3
terminals are used; and in S400 operation all D0D7 terminals are used for data transfer. When the TSB81BA3
is in control of the D0D7 bus, unused Dn terminals are driven low during S100 and S200 operations. When
the LLC is in control of the D0D7 bus, unused Dn terminals are ignored by the TSB81BA3.
The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access
to the serial-bus for packet transmission, read or write PHY registers, or control arbitration acceleration.
The LPS and LKON/DS2 terminals are used for power management of the PHY and LLC. The LPS terminal
indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable PCLK. The
LKON/DS2 terminal sends a wake-up notification to the LLC or external circuitry and indicates an interrupt to
the LLC when either LPS is inactive or the PHY register L bit is 0.
The TSB81BA3 normally controls the CTL0CTL1 and D0D7 bidirectional buses. The LLC is allowed to drive
these buses only after the LLC has been granted permission to do so by the PHY.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB81BA3IPFP | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3IPFPEP | 功能描述:射頻收發(fā)器 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3PFP | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3PFPG4 | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB82AA2 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394b OHCI-LYNX CONTROLLER |
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