參數(shù)資料
型號： TSB81BA3I
廠商： Texas Instruments, Inc.
英文描述： IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
中文描述： 的IEEE 1394b三端口電纜收發(fā)器/仲裁者
文件頁數(shù)： 41/57頁
文件大?。?/td> 810K
代理商： TSB81BA3I
SLLS559B DECEMBER 2002 REVISED OCTOBER 2003
41
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394a2000 INTERFACE)
interface reset and disable (continued)
SYSCLK
ISO
(high)
(a)
(c)
(b)
CTL0
D0 D7
LREQ
LPS
(d)
TCLK_ACTIVATE
CTL1
7 Cycles
Figure 19. Interface Initialization
The sequence of events for initialization of the PHY-LLC is as follows:
(a) LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum
T
RESTORE
time, the LLC causes the interface to be initialized and restored to normal operation by
reasserting the LPS signal. (In the above diagram, the interface is shown in the disabled state with PCLK
low inactive. However, the interface initialization sequence described here is also executed if the interface
is merely reset but not yet disabled.)
(b) PCLK activated. If the interface is disabled, then the PHY reactivates its PCLK output when it detects that
LPS has been reasserted. If the PHY has entered a low-power state, then it takes between 5.3 to 7.3 ms
for PCLK to be restored; if the PHY is not in a low-power state, then the PCLK is restored within 60 ns. The
PCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz
±
100 ppm (period of
20.345 ns). During the first 7 cycles of PCLK, the PHY continues to drive the CTL and D terminals low. The
LLC is also required to drive its CTL and D outputs low for 1 of the first 6 cycles of PCLK but to otherwise
place its CTL and D outputs in a high-impedance state. The LLC continues to drive its LREQ output low
during this time.
(c) Receive indicated. Upon the eighth PCLK cycle following reassertion of LPS, the PHY asserts the receive
state on the CTL lines and the data-on indication (all 1s) on the D lines for one or more cycles.
(d) Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This
indicates that the PHY-LLC interface initialization is complete and normal operation may commence. The
PHY now accepts requests from the LLC via the LREQ line.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB81BA3IPFP 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray
TSB81BA3IPFPEP 功能描述:射頻收發(fā)器 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray
TSB81BA3PFP 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray
TSB81BA3PFPG4 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray
TSB82AA2 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394b OHCI-LYNX CONTROLLER
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