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參數(shù)資料
| 型號： | TSB81BA3I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| 中文描述： | 的IEEE 1394b三端口電纜收發(fā)器/仲裁者 |
| 文件頁數(shù)： | 2/57頁 |
| 文件大?。?/td> | 810K |
| 代理商： | TSB81BA3I |
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SLLS559B DECEMBER 2002 REVISED OCTOBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description
The TSB81BA3 provides the digital and analog transceiver functions needed to implement a three-port node
in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB81BA3 is designed to interface
with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4,
TSB42AB4, TSB12LV01B, or TSB12LV01C. It may also be connected cable port to cable port to an integrated
1394 Link + PHY layer such as the TSB43AB2.
The TSB81BA3 is powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage
supply is supplied to the PLLVDD-1.8 and DVDD-1.8 terminals to the requirements in the recommended
operating conditions. The PLLVDD-1.8 terminals must be separated from the DVDD-1.8 terminals, the
PLLVDD-1.8 terminals are decoupled with 1
μ
F and smaller decoupling capacitors, and the DVDD-1.8 terminals
separately decoupled with a 1
μ
F and smaller decoupling capacitors. The separation between DVDD-1.8 and
PLLVDD-1.8 may be implemented by separate power supply rails, or by a single power supply rail, where the
DVDD-1.8 and PLLVDD-1.8 are separated by a filter network to keep noise from the PLLVDD-1.8 supply.
The TSB81BA3 requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external
clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference
signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz
clock signal is supplied to the associated LLC for synchronization of the two devices and is used for
resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE
1394a2000 standard. A 98.304-MHz clock signal is supplied to the associated LLC for synchronization of the
two devices when operating the PHY-link interface in compliance with the IEEE P1394b standard. The power
down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.
Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths
(depending on the requested transmission speed and PHY-link interface mode of operation). They are latched
internally, combined serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbits/s
(referred to as S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream.
The PHY-link interface can follow either the IEEE 1394a2000 protocol or the IEEE 1394b2002 protocol. When
using a 1394a2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link
interface then operates in accordance with the legacy 1394a2000 standard. When using a 1394b LLC such
as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the P1394b
standard.
The cable interface can follow either the IEEE 1394a2000 protocol or the 1394b protocol on all ports. The mode
of operation is determined by the interface capabilities of the ports being connected. When any of the three ports
is connected to a 1394a2000 compliant device, the cable interface on that port operates in the 1394a2000
data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b
compliant node, the cable interface on that port operates per the P1394b standard at S400B or S800 speed.
The TSB81BA3 automatically determines the correct cable interface connection method for the bilingual ports.
NOTE:
The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal
selects the PHY-link interface mode of operation and affects the arbitration modes on the cable.
When the BMODE terminal is deasserted, BOSS arbitration is disabled.
During packet reception the serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon
the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system
clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected
and active cable ports.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB81BA3IPFP | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3IPFPEP | 功能描述:射頻收發(fā)器 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3PFP | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3PFPG4 | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB82AA2 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394b OHCI-LYNX CONTROLLER |
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