參數(shù)資料
型號(hào)： TSB81BA3I
廠商： Texas Instruments, Inc.
英文描述： IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
中文描述： 的IEEE 1394b三端口電纜收發(fā)器/仲裁者
文件頁(yè)數(shù)： 16/57頁(yè)
文件大小： 810K
代理商： TSB81BA3I
SLLS559B DECEMBER 2002 REVISED OCTOBER 2003
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table 2. Base Register Field Descriptions (Continued)
FIELD
SIZE
1
TYPE
Rd/Wr
DESCRIPTION
LCtrl
Link-active status control. This bit controls the indicated active status of the LLC reported in the self-ID packet.
The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The
LLC bit in the node self-ID packet is set active only if both the LPS input is active and the LCtrl bit is set.
The LCtrl bit provides a software controllable means to indicate the LLC self-ID active status in lieu of using the
LPS input terminal.
The LCtrl bit is set to 1 by hardware reset and is unaffected by bus-reset.
NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the
LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, then received
packets and status information continue to be presented on the interface, and any requests indicated on the
LREQ input are processed, even if the LCtrl bit is cleared to 0.
C
1
Rd/Wr
Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager.
This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to 0 on hardware reset. After
hardware reset, this bit may only be set via a software register write. This bit is unaffected by a bus reset.
PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest repeater data
delay, expressed as (jitter+1)
×
20 ns. For the TSB81BA3, this field is 0.
Node power class. This field indicates this node power consumption and source characteristics and is
replicated in the pwr field (bits 2123) of the self-ID packet. This field is reset to the state specified by the
PC0PC2 input terminals upon a hardware reset, and is unaffected by a bus reset. See Table 9.
Jitter
3
Rd
Pwr_Class
3
Rd/Wr
WDIE
1
Rd/Wr
Watchdog interrupt enable. This bit, if set to 1, enables the port event interrupt (PIE) bit to be set whenever
resume operations begin on any port, or when any of the CTOI, CPSI, or STOI interrupt bits are set and the link
interface is nonoperational. This bit is reset to 0 by hardware reset and is unaffected by bus reset.
Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3
μ
s) arbitrated bus
reset at the next opportunity. This bit is reset to 0 by a bus reset. It is recommended that short bus reset is the
only reset type initiated by software. IEC 61883-6 requires that a node initiate short bus resets to minimize any
disturbance to an audio stream.
NOTE: Legacy IEEE Std 13941995 compliant PHYs are not capable of performing short bus resets.
Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus
reset being performed.
Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-ID start,
and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset, or by writing a 1 to
this register bit.
If the CTOI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the
LKON/DS2 output to notify the LLC to service the interrupt.
NOTE: If the network is configured in a loop, then only those nodes which are part of the loop generate a
configuration-timeout interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID process to
complete and then generate a state time-out interrupt and bus-reset. This bit is only set when the bus topology
includes 1394a nodes; otherwise, 1394b loop healing prevents loops from being formed in the topology.
Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low indicating
that cable power may be too low for reliable operation. This bit is reset to 1 by hardware reset. It can be cleared
by writing a 1 to this register bit.
If the CPSI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the
LKON/DS2 output to notify the LLC to service the interrupt.
State-timeout interrupt. This bit indicates that a state time-out has occurred (which also causes a bus-reset to
occur). This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit.
If the STOI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the
LKON/DS2 output to notify the LLC to service the interrupt.
Port event interrupt. This bit is set to 1 on any change in the connected, bias, disabled, or fault bits for any port
for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt enable (WDIE) bit is
set, then the PEI bit is set to 1 at the start of resume operations on any port. This bit is reset to 0 by hardware
reset, or by writing a 1 to this register bit.
ISBR
1
Rd/Wr
CTOI
1
Rd/Wr
CPSI
1
Rd/Wr
STOI
1
Rd/Wr
PEI
1
Rd/Wr
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TSB82AA2 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:1394b OHCI-LYNX CONTROLLER
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