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參數(shù)資料
| 型號(hào)： | TSB81BA3I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| 中文描述： | 的IEEE 1394b三端口電纜收發(fā)器/仲裁者 |
| 文件頁數(shù)： | 7/57頁 |
| 文件大?。?/td> | 810K |
| 代理商： | TSB81BA3I |
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SLLS559B DECEMBER 2002 REVISED OCTOBER 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AGND
TYPE
Supply
NO.
21, 40, 43,
50, 61, 62
Analog circuit ground terminals. These terminals must be tied together to the low-impedance circuit
board ground plane.
AVDD3.3
Supply
24, 39, 44,
51, 57, 63
Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each
terminal are suggested, such as paralleled 0.1
μ
F and 0.001
μ
F. Lower frequency 10-
μ
F filtering
capacitors are also recommended. These supply terminals are separated from the PLLVDD-1.8,
PLLVDD-3.3, DVDD-1.8, and DVDD-3.3 terminals internal to the device to provide noise isolation.
The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied together with a low dc
impedance connection on the circuit board.
BMODE
CMOS
74
I
Beta-mode input. This terminal determines the PHY-link interface connection protocol. When logic
high (asserted), the PHY-link interface complies with the P1394b revision 1.33 standard B PHY-link
interface. When logic low (deassered), the PHY-link interface complies with the legacy 1394a2000
standard. When using a LLC such as the 1394b TSB82AA2, this terminal must be pulled high. When
using a LLC such as the 1394a2000 TSB12LV26, this terminal must be tied low.
NOTE: The PHY-link interface cannot be changed between the different protocols during operation.
CNA
CMOS
79
O
Cable not active output. This terminal is asserted high when there are no ports receiving incoming
bias voltage. When any port receives bias, this terminal goes low.
CPS
CMOS
34
I
Cable power status input. This terminal is normally connected to cable power through a 400-k
resistor. This circuit drives an internal comparator that detects the presence of cable power. This
transition from cable power sensed to cable power not sensed may be used to generate an interrupt
to the LLC.
CTL0
CTL1
CMOS
9
10
I/O
Control I/Os. These bidirectional signals control communication between the TSB81BA3 and the
LLC. Bus holders are built into these terminals.
D0D7
CMOS
11, 12, 13,
15, 16, 17,
19, 20
I/O
Data I/Os. These are bidirectional data signals between the TSB82BA3 and the LLC. Bus holders
are built into these terminals.
DGND
Supply
4, 14, 38,
64, 72, 76
Digital circuit ground terminals. These terminals must be tied together to the low-impedance circuit
board ground plane.
DS0
CMOS
33
I
Data-strobe-only mode for port 0. 1394a-only port 0 enable programming terminal. On hardware
reset, this terminal allows the user to select whether port 0 acts like a 1394b bilingual port (terminal at
logic 0) or as a 1394a2000-only port (terminal at logic 1). Programming is accomplished by tying the
terminal low through a 1-k
or less resistor (to enable 1394b bilingual mode) or high through a 1-k
or less resistor (to enable 1394a2000-only mode). A bus holder is built into this terminal.
DS1
CMOS
32
I
Data-strobe-only mode for port 1. 1394a-only port 1 enable programming terminal. On hardware
reset, this terminal allows the user to select whether port 1 acts like a 1394b bilingual port (terminal at
logic 0) or as a 1394a2000-only port (terminal at logic 1). Programming is accomplished by tying the
terminal low through a 1-k
or less resistor (to enable 1394b bilingual mode) or high through a 1-k
or less resistor (to enable 1394a2000-only mode). A bus holder is built into this terminal.
DVDD-1.8
Supply
8, 37, 65,
71
Digital 1.8-V circuit power terminals. A combination of high-frequency decoupling capacitors near
each terminal are suggested, such as paralleled 0.1
μ
F and 0.001
μ
F. An additional 1-
μ
F capacitor is
required for voltage regulation. These supply terminals are separated from the DVDD-3.3,
PLLVDD-1.8, PLLVDD-3.3, and AVDD-3.3 terminals internal to the device to provide noise isolation.
DVDD-3.3
Supply
6, 18, 69,
70
Digital 3.3-V circuit power terminals. A combination of high-frequency decoupling capacitors near
each terminal are suggested, such as paralleled 0.1
μ
F and 0.001
μ
F. Lower frequency 10-
μ
F
filtering capacitors are also recommended. The DVDD-3.3 terminals must be tied together at a
low-impedance point on the circuit board. These supply terminals are separated from the
PLLVDD-1.8, PLLVDD-3.3, DVDD-1.8, and AVDD-3.3 terminals internal to the device to provide
noise isolation. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied together with a
low dc impedance connection on the circuit board.
LCLK
CMOS
7
I
Link clock. Link-provided 98.304-MHz clock signal to synchronize data transfers from link to the PHY
when the PHY-link interface is in the 1394b mode. A bus holder is built into this terminal.
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| TSB81BA3IPFP | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3IPFPEP | 功能描述:射頻收發(fā)器 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3PFP | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3PFPG4 | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB82AA2 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394b OHCI-LYNX CONTROLLER |
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