參數(shù)資料
型號(hào)： TSB81BA3I
廠商： Texas Instruments, Inc.
英文描述： IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
中文描述： 的IEEE 1394b三端口電纜收發(fā)器/仲裁者
文件頁(yè)數(shù)： 38/57頁(yè)
文件大小： 810K
代理商： TSB81BA3I
SLLS559B DECEMBER 2002 REVISED OCTOBER 2003
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394a2000 INTERFACE)
transmit (continued)
The sequence of events for a cancelled/null packet transmission is as follows:
(a) Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the
interface to the link.
(b) Optional idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle
is optional; the link is not required to assert idle preceding hold.
(c) Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of idle. These hold
cycle(s) are optional; the link is not required to assert hold preceding idle.
(d) Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of idle
on the CTL lines and then releasing the interface and returning control to the PHY. Note that the link may
assert idle for a total of three consecutive cycles if it asserts the optional first idle cycle but does not assert
hold. It is recommended that the link assert three cycles of idle to cancel a packet transmission if no hold
cycles are asserted. This ensures that either the link or PHY controls the interface in all cycles.
(e) After regaining control of the interface, the PHY asserts at least one idle cycle before any subsequent status
transfer, receive operation, or transmit operation.
interface reset and disable
The LLC controls the state of the PHY-LLC interface using the LPS signal. The interface may be placed into a
reset state, a disabled state, or be made to initialize and then return to normal operation. When the interface
is not operational (whether reset, disabled, or in the process of initialization), the PHY cancels any outstanding
bus request or register read request, and ignores any requests made via the LREQ line. Additionally, any status
information generated by the PHY is not queued and does not cause a status transfer upon restoration of the
interface to normal operation.
The LPS signal may be either a level signal or a pulsed signal, depending upon whether the PHY-LLC interface
is a direct connection or is made across an isolation barrier. When an isolation barrier exists between the PHY
and LLC the LPS signal must be pulsed. In a direct connection, the LPS signal may be either a pulsed or a level
signal. Timing parameters for the LPS signal are given in Table 21.
Table 21. LPS Timing Parameters
PARAMETER
TLPSL
DESCRIPTION
MIN
0.09
0.021
20%
2.60
26.03
MAX
2.60
2.60
60%
2.68
26.11
23
UNIT
μ
s
μ
s
LPS low time (when pulsed) (see Note 5)
LPS high time (when pulsed) (see Note 5)
LPS duty cycle (when pulsed) (see Note 6)
Time for PHY to recognize LPS deasserted and reset the interface
Time for PHY to recognize LPS deasserted and disable the interface
Time to permit optional isolation circuits to restore during an interface reset
TLPSH
TLPS_RESET
TLPS_DISABLE
TRESTORE
μ
s
μ
s
μ
s
ns
ms
15
TCLK_ACTIVATE
Time for PCLK to be activated from reassertion of LPS
PHY not in low-state
PHY in low-power state
60
7.3
5.3
The maximum value for TRESTORE does not apply when the PHY-LLC interface is disabled, in which case an indefinite time may elapse before
LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is deasserted for less
than TLPS_DISABLE.
NOTES:
3. The specified TLPSL and TLPSH times are worst-case values appropriate for operation with the TSB81BA3. These values are broader
than those specified for the same parameters in the 1394a2000 Supplement (that is, an implementation of LPS that meets the
requirements of 1394a2000 operates correctly with the TSB81BA3).
4. A pulsed LPS signal must have a duty cycle (ratio of TLPSH to cycle period) in the specified range to ensure proper operation when
using an isolation barrier on the LPS signal (for example, as shown in Figure 8).
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TSB81BA3PFP 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類(lèi)型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類(lèi)型:SPI 封裝 / 箱體:QFN-32 封裝:Tray
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TSB82AA2 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394b OHCI-LYNX CONTROLLER
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