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參數(shù)資料
| 型號(hào)： | TSB81BA3I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| 中文描述： | 的IEEE 1394b三端口電纜收發(fā)器/仲裁者 |
| 文件頁數(shù)： | 49/57頁 |
| 文件大?。?/td> | 810K |
| 代理商： | TSB81BA3I |
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SLLS559B DECEMBER 2002 REVISED OCTOBER 2003
49
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394B INTERFACE)
receive
When the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting receive
on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The PHY indicates the start
of a packet by placing the speed code (encoded as shown in Table 35) on the D terminals, followed by packet
data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet has been
transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All received
packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included
in the calculation of CRC or any other data protection mechanisms.
The PHY may optionally send status information to the LLC at anytime during the data-on indication. Only bus
status transfer information can be sent during a data-on indication. The PHY holds the CTL terminals in the
status state for 1 PCLK cycle and modify the D terminals to the correct status state. Note that the status transfer
during the data-on indication does not need to be preceded or followed by a data-on indication.
It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed
by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds
the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any
data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D
terminals, followed by Idle on the CTL terminals, without any speed code or data being transferred. In all cases,
in normal operation, the TSB81BA3 sends at least one data-on indication before sending the speed code or
terminating the receive operation.
The TSB81BA3 also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization,
to the LLC. This packet it transferred to the LLC just as any other received self-ID packet.
00
00
10
XX
dn
d0
SPD
(a)
(b)
FF (data-on)
D0–D7
CTL0, CTL1
PCLK
(c)
(d)
(e)
NOTE A: SPD = Speed code, see Table 35. d0–dn = Packet data
Figure 24. Normal Packet Reception Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB81BA3IPFP | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3IPFPEP | 功能描述:射頻收發(fā)器 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3PFP | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3PFPG4 | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB82AA2 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394b OHCI-LYNX CONTROLLER |
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