參數(shù)資料
型號: TSB81BA3I
廠商: Texas Instruments, Inc.
英文描述: IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
中文描述: 的IEEE 1394b三端口電纜收發(fā)器/仲裁者
文件頁數(shù): 17/57頁
文件大?。?/td> 810K
代理商: TSB81BA3I
SLLS559B DECEMBER 2002 REVISED OCTOBER 2003
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table 2. Base Register Field Descriptions (Continued)
FIELD
SIZE
1
TYPE
Rd/Wr
DESCRIPTION
EAA
Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration
enhancements defined in 1394a2000 (ACK-accelerated arbitration, asynchronous fly-by concatenation, and
isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus reset. This
bit has no effect when the device is operating in 1394b mode.
NOTE: The use of accelerated arbitration is completely compatible with networks containing legacy IEEE Std
13941995 PHYs. The EAA bit is set only if the attached LLC is 1394a2000 or 1394b2002 compliant. If the
LLC is not 1394a2000 compliant, then the use of the arbitration acceleration enhancements can interfere with
isochronous traffic by excessively delaying the transmission of cycle-start packets.
Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of
differing speeds in accordance with the protocols defined in 1394a2000. This bit is reset to 0 by hardware
reset and is unaffected by bus reset. This bit has no effect when the device is operating in 1394b mode.
NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy IEEE
Std 13941995 PHYs. However, use of multispeed concatenation requires that the attached LLC be
1394a2000 or 1394b2002 compliant.
Maximum legacy-path speed. This field holds the maximum speed capability of any legacy node (1394a2000
or 13941995 compliant) as indicated in the self-ID packets received during bus-initialization. Encoding is the
same as for the PHY_SPEED field (but limited to S400 maximum).
Beta-mode link. This bit indicates that a beta-mode capable link is attached to the PHY. This bit is set by the
BMODE input terminal on the TSB81BA3.
This field controls the value of the bridge (brdg) field in self-ID packet. The power reset value is 0. Details for
when to set these bits are specified in the IEEE 1394.1 bridging specification.
Page_Select. This field selects the register page to use when accessing register addresses 8 through 15. This
field is reset to 0 by a hardware reset and is unaffected by bus-reset.
Port_Select. This field selects the port when accessing per-port status or control (for example, when one of the
port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset to 0 by
hardware-reset and is unaffected by bus-reset.
EMC
1
Rd/Wr
Max Legacy
SPD
3
Rd
BLINK
1
Rd
Bridge
2
Rd/Wr
Page_Select
3
Rd/Wr
Port_Select
4
Rd/Wr
The port status page provides access to configuration and status information for each of the ports. The port is
selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base
register 7. Table 3 shows the configuration of the port status page registers, and Table 4 gives the corresponding
field descriptions. If the selected port is unimplemented, then all registers in the port status page are read as
0.
Table 3. Page 0 (Port Status) Register Configuration
BIT POSITION
Address
0
1
2
3
4
5
6
7
1000
Astat
BStat
Ch
Con
RXOK
Dis
1001
Negotiated_speed
PIE
Fault
Standby_fault
Disscrm
B_Only(0)
1010
DC_connected
Max_port_speed (011b)
LPP
Cable_speed
1011
Connection_unreliable
Reserved
Beta_mode
Reserved
1100
Port_error
1101
Reserved
Loop_disable
In_standby
Hard_disable
1110
Reserved
1111
Reserved
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