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參數(shù)資料
| 型號： | TSB81BA3I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| 中文描述： | 的IEEE 1394b三端口電纜收發(fā)器/仲裁者 |
| 文件頁數(shù)： | 26/57頁 |
| 文件大?。?/td> | 810K |
| 代理商： | TSB81BA3I |
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SLLS559B DECEMBER 2002 REVISED OCTOBER 2003
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
power-up reset
To ensure proper operation of the TSB81BA3 the RESETz terminal must be asserted low for a minimum of 2 ms
from the time that PHY power reaches the minimum required supply voltage. When using a passive capacitor
on the RESETz terminal to generate a power-on reset signal, the minimum reset time is assured if the value
of the capacitor satisfies the following equation (the value must be no smaller than approximately 0.1
μ
F):
C
min
= 0.0077
×
T + 0.085 + external_oscillator_start-up_time
where C
min
is the minimum capacitance on the RESETz terminal in
μ
F, T is the V
DD
ramp time, 10%90%, in
ms, external_oscillator_start-up_time is the time from power applied to the external oscillator till the oscillator
outputs a valid clock in ms.
crystal oscillator selection
The TSB81BA3 is designed to use an external 98.304-MHz crystal oscillator connected to the XI terminal to
provide the reference clock. This clock, in turn, drives a PLL circuit that generates the various clocks required
for transmission and resynchronization of data at the S100 through S800 media data rates.
A variation of less than
±
100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent
PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must
be able to compensate for this difference over the maximum packet length. Larger clock variations may cause
resynchronization overflows or underflows, resulting in corrupted packet data.
For the TSB81BA3, the PCLK output may be used to measure the frequency accuracy and stability of the
internal oscillator and PLL from which it is derived. When operating the PHY-LLC interface with a non-1394b
LLC, the frequency of the PCLK output must be within
±
100 ppm of the nominal frequency of 49.152 MHz. When
operating the PHY-LLC interface with a 1394b LLC, the frequency of the PCLK output must be within
±
100 ppm
of the nominal frequency of 98.304 MHz.
The following are some typical specifications for an oscillator used with the TSB81BA3 physical layer from TI in
order to achieve the required frequency accuracy and stability:
RMS jitter of 5 picoseconds or better
RMS phase noise jitter of 1 picosecond or less over the range 12 kHz to 20 MHz or better
Frequency tolerance at 25 C: Total frequency variation for the complete circuit is
±
100 ppm. A device with
±
30 ppm or
±
50 ppm frequency tolerance is recommended for adequate margin.
Frequency stability (over temperature and age): A device with
±
30 ppm or
±
50 ppm frequency stability is
recommended for adequate margin.
NOTE:
The total frequency variation must be kept below
±
100 ppm from nominal with some allowance for
error introduced by board and device variations. Trade-offs between frequency tolerance and
stability may be made as long as the total frequency variation is less than
±
100 ppm. For example,
the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance
may be specified at 30 ppm to give a total of 80 ppm possible variation due to the oscillator alone.
Aging also contributes to the frequency variation.
It is strongly recommended that part of the verification process for the design is to measure the frequency of the
PCLK output of the PHY. This should be done with a frequency counter with an accuracy of 6 digits or better.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB81BA3IPFP | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3IPFPEP | 功能描述:射頻收發(fā)器 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3PFP | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB81BA3PFPG4 | 功能描述:射頻收發(fā)器 s800 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TSB82AA2 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394b OHCI-LYNX CONTROLLER |
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