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參數(shù)資料
| 型號： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動柜員機接收器/發(fā)送器為622.08，麻省理工學院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動柜員機接收器/傳送器） |
| 文件頁數(shù)： | 9/54頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | TNETA1600 |
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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
transmit operation
The TNETA1600 operates at either 155.52 Mbit/s or 622.08 Mbit/s. The choice of operation is made through
the EN155 input. When the device is programmed to operate at 155.52 Mbit/s, the device transmits a
STS-3c/STM-1 frame. When the device is programmed to operate at 622.08 Mbit/s, the device transmits a
STS-12c/STM-4c frame. Both the STS-3c/STM-1 and STS-12c/STM-4c outputs are byte wide.
transmit-cell interface
The transmit-cell interface consists of an 8-/16-bit-wide input data (TD0-TD15), input clock (TCKI), start of ATM
cell input (TXSOC), transmit write-enable input (TWE), and transmit cell-available output (TXCLAV). Input data
is clocked into the TNETA1600 on low-to-high transitions of TCKI when TWE is low. TXCLAV goes active when
the transmit input FIFO is capable of accepting the transfer of a complete ATM cell. TXCLAV goes inactive when
the transmit input FIFO is within four write cycles (four bytes during 155.52-Mbit/s operation or eight bytes during
622.08-Mbit/s operation) of being full. The FIFO holds three complete ATM cells. The reception of a high signal
on TXSOC indicates the first byte (or first two bytes in a 16-bit cell interface) of an ATM cell. Once the input FIFO
receives a high TXSOC signal indicating the start of an ATM cell, the interface ignores subsequent TXSOC
indications until each byte of the incoming ATM cell is received. Receiving a TXSOC indication in the middle
of a cell does not reset the input-byte counters and the device groups the first 53 bytes (54 bytes for 622-Mbit/s
operation) received after the initial TXSOC indication into a single ATM cell. The transmit-cell interface is fully
synchronous. All signals associated with the interface are either sampled or valid on the rising edge of TCKI.
The design goal for the interface is to operate at frequencies up to 50 MHz over worst-case supply voltage,
process control, and temperature. The data input on the transmit-cell interface is 16 bits wide for 622.08-Mbit/s
operation and 8 bits wide for 155.52-Mbit/s operation. The width of the datapath is set when the user chooses
either 155.52-Mbit/s or 622.08-Mbit/s operation through the EN155 input. For the 16-bit data input, the device
can be configured to accept data in two different input formats. For the first format, data is input as 54 bytes per
ATM cell with two user-defined bytes (UDBs) separating the four bytes of the ATM header from the cell payload.
The second format has one UDB separating the four bytes of the ATM header from the cell payload and a second
UDB at the end of the cell payload. These two formats are illustrated in Figure 1. In each format, the second
UBD is discarded so that the 53-byte ATM cell can be mapped into a SONET/SDH frame. The selection of the
data format is made via the control register, which is accessible through the controller interface. When a
hardware or software reset occurs, the device is set to accept format 1. For the 8-bit data interface, data is input
as a 53-byte ATM cell with one UDB separating the four bytes of the ATM header from the 48-byte cell payload.
FORMAT NO. 1
FORMAT NO. 2
MSB BITS 15
LSB BIT 0
MSB BIT 15
LSB BIT 0
Header Byte No. 1
Header Byte No. 2
Header Byte No. 1
Header Byte No. 2
Header Byte No. 3
Header Byte No. 4
Header Byte No. 3
Header Byte No. 4
UDB No. 1
UDB No. 2
UDB No. 1
Payload Byte No. 1
Payload Byte No. 1
Payload Byte No. 2
Payload Byte No. 2
Payload Byte No. 3
:
:
:
:
:
:
:
:
Payload Byte No. 47
Payload Byte No. 48
Payload Byte No. 48
UDB No. 2
Figure 1. Transmit-Cell Interface Formats for 16-Bit Input Data
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