參數(shù)資料
型號(hào)： TNETA1600
廠商： Texas Instruments, Inc.
英文描述： SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器)
中文描述： SONET / SDH的自動(dòng)柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動(dòng)柜員機(jī)接收器/傳送器）
文件頁(yè)數(shù)： 8/54頁(yè)
文件大?。?/td> 1120K
代理商： TNETA1600
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
JTAG test access port
TERMINAL
NAME
I/O
DESCRIPTION
NO.
TCK
I
Test clock. TCK is one of four terminals required by IEEE Standard 1149.1. TCK samples data on TDI,
outputs data on TDO, and clocks the test-access-port (TAP) controller. Data on the device inputs is captured
on the rising edge of TCK, and outputs change on the falling edge of TCK.
TDI
I
Test-data input. TDI is one of four terminals required by IEEE Standard 1149.1. TDI is the serial input for
shifting information into the instruction register or selected data register. TDI is captured on the rising edge
of TCK.
TDO
O
Test-data output. TDO is one of four terminals required by IEEE standard 1149.1. TDO is the serial output
for shifting information out of the instruction register or selected data register. TDO is updated on the falling
edge of TCK.
TMS
I
Test-mode select. TMS is one of four terminals required by IEEE Standard 11.49.1. TMS directs the TAP
controller through its states. TMS is captured on the rising edge of TCK.
TRST
I
Test reset. TRST is the active-low input that implements the optional reset terminal of IEEE Standard 1149.1.
When asserted (low), TRST causes the TAP controller to asynchronously enter the test-logic-reset state
and configure the instruction register and test data registers to their default values. A high-level on TRST
allows normal TAP controller operation. TRST should be held low during device power up.
miscellaneous signals
TERMINAL
NAME
I/O
DESCRIPTION
NO.
GND
Ground. GND1 is the 0-V reference for TTL circuits.
Supply voltage. VCC1 is the 5 V
±
5% supply for the TTL circuits.
Receive-side 8-kHz reference. Pulse duration is approximately 450 ns.
VCC
RXREF8K
O
TXREF8K
O
Transmit-side 8-kHz reference. Pulse duration is approximately 450 ns.
NC
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
All test mode inputs are mirrored by bits in the control registers. A logical OR function provides the resulting control signal. For example, the TX
SONET scrambler is disabled when a high-level signal is applied to TEST1 terminal or when the associated control register bit is set high for
the TX SONET scrambler.
No connection. These terminals are left open.
I
Test mode 0. TEST0 activates the short-frame test mode.
I
Test mode 1. TEST1 disables the TX SONET scrambler.
I
Test mode 2. TEST2 disables the RX SONET descrambler.
I
Test mode 3. TEST3 disables the TX ATM cell scrambler.
I
Test mode 4. TEST4 disables the RX ATM cell descrambler.
I
Test mode 5. TEST5 activates the UTOPIA loopback mode.
P
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