參數(shù)資料
型號(hào)： TNETA1600
廠商： Texas Instruments, Inc.
英文描述： SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器)
中文描述： SONET / SDH的自動(dòng)柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動(dòng)柜員機(jī)接收器/傳送器）
文件頁(yè)數(shù)： 21/54頁(yè)
文件大?。?/td> 1120K
代理商： TNETA1600
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
loss-of-optical carrier (LOPC)
This bit is set when LOPC goes high. The LOPC bit clears when LOPC goes low. This provides an interrupt
through the controller interface to the host indicating that the incoming optical signal was lost. A change in the
status bit in the status register for this alarm causes INTR output to go active. When the status bit makes a
low-to-high transition, the INTR output goes active. The INTR output also goes active when the status bit makes
a high-to-low transition. Reading the status register does not clear the status bit for this alarm. However, the
INTR output goes inactive on a read of any of the status registers. A hardware or software reset has no effect
on the state of this bit.
line-alarm-indication signal (LAIS)
This bit is set when the LAIS activation counter reaches a programmable value (one to fifteen) representing the
number of consecutive frames in which the condition occurs. The LAIS bit is cleared when the LAIS deactivation
counter reaches an independently programmable value (one to fifteen) representing the number of consecutive
frames occurring without the condition. The LAIS condition is detected by the counters as a 111 pattern in bits
6–8 of the K2 byte. A hardware of software reset causes this bit to clear. This bit is set as long as the LAIS
condition exists. When the logic in the TNETA1600 detects that the LAIS condition has cleared, the status bit
in the status register is cleared. A change in the status bit causes the INTR output to go active. When the status
bit makes a low-to-high transition, the INTR output goes active. The INTR output also goes active when the
status bit makes a high-to-low transition. Reading the status register does not clear the status bit for this alarm.
However, the INTR output goes inactive on a read of any of the status registers.
line far-end receive failure (LFERF)
This bit is set when the LFERF activation counter reaches a programmable value (one to fifteen) representing
the number of consecutive frames in which the condition occurs. The LFERF is cleared when the LFERF
deactivation counter reaches an independently programmable value (one to fifteen) representing the number
of consecutive frames occurring without the condition. The LFERF condition is detected by the counters as a
110 pattern in bits 6–8 of the K2 byte. A hardware or software reset causes this bit to clear. This bit is set as
long as the LFERF condition exists. When the logic in the TNETA1600 detects that the LFERF condition has
cleared, the status bit in the status register is cleared. A change in the status bit causes the INTR output to go
active. When the status bit makes a low-to-high transition, the INTR output goes active. The INTR output also
goes active when the status bit makes a high-to-low transition. Reading the status register does not clear the
status bit for this alarm. However, the INTR output goes inactive on a read of any of the status registers.
loss-of-received data (LOSRD)
This bit is set when the receive output FIFO overflows. The output FIFO can store three complete ATM cells.
However, if a cell is not removed from the output FIFO before a fourth cell arrives, the arriving cell is discarded.
This bit is cleared when an incoming cell is not discarded due to a full FIFO. A hardware or software reset causes
this bit to be cleared. This bit is set as long as the LOSRD condition exists. When the logic in the TNETA1600
detects that the LOSRD condition has cleared, the status bit in the status register is cleared. A change in the
status bit causes INTR output to go active. When the status bit makes a low-to-high transition, the INTR output
goes active. The INTR output also goes active when the status bit makes a high-to-low transition. Reading the
status register does not clear the status bit for this alarm. However, the INTR output goes inactive on a read
of any of the status registers.
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TNETA1611PCA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Transceiver
TNETA1622 制造商:TI 制造商全稱:Texas Instruments 功能描述:622.08-MHz CLOCK-RECOVERY DEVICE
TNETA1622DW 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock/Data Recovery
TNETA1630DW 制造商:Texas Instruments 功能描述:
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