參數(shù)資料
型號(hào)： TNETA1600
廠商： Texas Instruments, Inc.
英文描述： SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器)
中文描述： SONET / SDH的自動(dòng)柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動(dòng)柜員機(jī)接收器/傳送器）
文件頁數(shù)： 39/54頁
文件大小： 1120K
代理商： TNETA1600
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
39
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
run-test/idle
The controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. the Run-Test/Idle state can also be entered following data-register (DR) or instruction-register (IR)
scans. This is a stable state in which the test logic is idle.
select-DR-scan, select-IR-scan
No specific function is performed in these states and the TAP controller exits either of these states on the next
TCK cycle. These states allow the selection of either data-register scan or instruction-register scan.
capture-DR
In the Capture-DR state, the selected data register can capture a data value as specified by the current
instruction. Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits this
state.
shift-DR
In the Shift-DR state, the selected test-data register shifts by one stage on the rising edge of TCK. Shifting is
from most-significant bit (the bit nearest TDI) to least-significant bit (the bit nearest TDO).
exit1-DR, exit2-DR
These states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state
from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK after entry
to Exit1-DR, TDO goes from the active state to the high-impedance state.
pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state can suspend and resume data-register scan operations without loss of data.
update-DR
If the current instruction calls for the selected data register to be updated with current data, such an update
occurs on the falling edge of TCK following entry into the Update-DR state.
capture-IR
In the Capture-IR state, the instruction register captures the fixed binary value 1000 0001. The capture occurs
on the rising edge of TCK, upon which the TAP controller exits this state.
shift-IR
In the Shift-IR state, the instruction register shifts by one stage on the rising edge of TCK. Shifting is from
most-significant bit (the bit nearest TDI) to least-significant bit (the bit nearest TDO).
exit1-IR, exit2-IR
These states are temporary states that end an instruction-register scan. It is possible to return to the Shift-IR
state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the first falling edge of TCK
after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.
pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state can suspend and resume instruction-register scan operations without loss of
data.
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TNETA1622DW 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock/Data Recovery
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