
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
force-transmit line AIS
When set to a high level, this bit causes the insertion of valid SOH and a scrambled all-ones pattern for the
remainer of the transmit signal. Also, ATM cells input to the transmit FIFO are not inserted into the outgoing
frame. Once the FIFO is full, the device does not accept additional data on the transmit input until the device
is returned to normal operating mode. When this bit is low, normal processing occurs. When a reset operation
is performed, this bit is cleared (set to 0).
force-transmit line FERF
When set to a high level, this bit causes the insertion of a 110 in bits 6–8 of the transmit K2 byte. When this bit
is low, normal processing dictates the values inserted in bits 6–8 of the K2 byte. When a reset operation is
performed, this bit is cleared (set to 0).
force-transmit path FERF
When set to a high level, this bit causes the insertion of a 1001 pattern in bits 1–4 of the transmit G1 byte. When
this bit is low, normal processing dictates the values inserted in bits 1–4 of the G1 byte. When a reset operation
is performed, this bit is cleared (set to 0).
enable LOCA to path RDI soak count
When set to a high level, this bit enables the LOCA to path-RDI soak counter such that a persistent LOCA
condition causes the automatic generation of a path RDI. When this bit is low, a persistent LOCA condition does
not cause the transmission of a path RDI. When a reset operation occurs, this bit is cleared. The normal
operation of the TNETA1600 is not to generate a path RDI as a result of a persistent LOCA condition.
force-transmit path AIS
When set to a high level, this bit causes the insertion of an all-ones signal in H1, H2, H3, and the entire transmit
synchronous payload envelope (SPE) before scrambling. All transport-overhead bytes, other than H1–H3, are
calculated and inserted normally. However, the receiving station is not able to locate the SPE and path-overhead
bytes, since the pointer bytes are all ones. Also, ATM cells input to the transmit FIFO are not inserted into the
outgoing frame. Once the FIFO is full, the device does not accept additional data on the transmit input until the
device is returned to normal operating mode. When this bit is low, normal processing occurs. When a reset
operation is performed, this bit is cleared (set to 0).
disable receive
SONET descrambler
This bit is logically ORed with the TEST2 terminal. If either or both are set to a high level, SONET descrambling
(x
7
+ x
6
+ 1) in the receiver is disabled. When a reset operation is performed, this bit is cleared (set to 0). The
normal operating state of the TNETA1600 is to provide SONET descrambling in the receiver; an action must
be taken to disable this function.
disable receive
ATM descrambler
This bit is logically ORed with the TEST4 terminal. If either or both are set to a high level, ATM descrambling
(x
43
+ 1) in the receiver is disabled. When a reset operation is performed, this bit is cleared (set to 0). The normal
operating state of the TNETA1600 is to provide ATM descrambling in the receiver; an action must be taken to
disable this function.
disable transmit
SONET scrambler
This bit is logically ORed with the TEST1 terminal. If either or both are set to a high level, SONET scrambling
(x
7
+ x
6
+ 1) in the transmitter is disabled. When a reset operation is performed, this bit is cleared (set to 0). The
normal operating state of the TNETA1600 is to provide SONET scrambling in the transmitter; an action must
be taken to disable this function.
P