參數資料
型號: TNETA1600
廠商: Texas Instruments, Inc.
英文描述: SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器)
中文描述: SONET / SDH的自動柜員機接收器/發(fā)送器為622.08,麻省理工學院/ s或155.52 - Mbit / s的操作(SONET / SDH的自動柜員機接收器/傳送器)
文件頁數: 46/54頁
文件大?。?/td> 1120K
代理商: TNETA1600
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
46
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements (see Figure 6)
NO.
MIN
MAX
UNIT
1
tsu(TDEN)
Setup time, TDEN
before TCO
ns
2
tsu(TSDI)
Setup time, TSDI valid before TCO
ns
3
th(TDEN)
Hold time, TDEN
before TCO
ns
4
th(TSDI)
Hold time, TSDI valid after TCO
ns
operating characteristics (see Figure 6)
NO.
PARAMETER
MIN
MAX
UNIT
5
tw(TCOH)
Pulse duration, TCO high
ns
6
tw(TCOL)
Pulse duration, TCO low
ns
7
td(TFPO)
Delay time, TCO
to TFPO
ns
TSDI
(Input)
TFPO
(output)
TCO
(output)
5
TDEN
(Input)
4
7
3
6
1
1st Clock of Cycle
113th Clock of Cycle
1st Clock of Cycle
E1, Bit 1
(MSB)
E1, Bit 2
E1, Bit 3
See Note A
NOTE A: The state of TDEN is examined by TNETA1600 on the rising edge of TCO associated with the first bit (MSB) of each orderwire and
data-communications byte. When TDEN is high on the first bit of the particular byte, that entire byte is read on TSDI. When TDEN is
low on the first bit, TSDI is ignored for the eight clock cycles associated with that byte and that byte retains the value existing in overhead
RAM. TDEN is reexamined on the first bit of the next byte.
Figure 6. Transmit Data-Communications Interface
P
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