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參數(shù)資料
| 型號： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動柜員機接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動柜員機接收器/傳送器） |
| 文件頁數(shù)： | 16/54頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | TNETA1600 |
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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
receive operation (continued)
Next, ATM cells are identified and extracted. Cell delineation is accomplished by computing the header error
check (HEC) value for the first four bytes of the payload and comparing the calculated value with the fifth byte.
If the values do not match, the process advances one byte and is repeated. This process continues until a match
between the calculated value and the fifth byte occurs. Cell alignment is assumed to occur when seven
consecutive matches occur on cell boundaries. Until cell alignment occurs, the loss of cell alignment (LOCA)
alarm remains active. Once cell alignment is established, it is monitored constantly for a LOCA condition. A
LOCA condition is declared (LOCA goes active) when seven consecutive cells occur with a mismatch between
the calculated HEC and the fifth byte of the ATM header. At this point, the hunting process starts over.
The receive side provides the capability to detect multiple bit errors and correct single bit errors occurring in the
5-byte ATM header by using the HEC byte. This feature is deactivated by setting a bit in the control register.
ATM cells with multiple-bit header errors are dropped after descrambling, unless a bit is set in the control register
to disable the dropping of cells with uncorrectable errors. Two 16-bit counters (accessible through the controller
interface) are provided to kept EDAC statistics. One counter accumulates the number of ATM cells with single
bit errors. A second counter accumulates the number of ATM cells that are received with multiple bit errors.
When any of the counters reach maximum count, a bit is set in the status register and an interrupt is generated.
These counters are rollover counters, (i.e., they roll over to zero after the maximum count occurs and an interrupt
is generated).
After the ATM cells are extracted, they are descrambled. The 48-byte payload in the ATM cell is scrambled at
the transmitter using a x
43
+ 1 polynomial to further distinguish the payload from the header bytes and improve
the efficiency of the cell-delineation algorithm. The x
43
+ 1 polynomial is also used to descramble the payload
so that it can be sent to the next device.
The TNETA1600 provides the capability of dropping idle and unassigned cells from the receive data stream.
An idle cell is defined as a cell with the 5-byte ATM header set to a value of 00 00 00 01 52 (hex) and an
unassigned cell is defined as a cell with a 5-byte header of 00 00 00 00 55 (hex). In both cases, the payload
is ignored. To identify and treat a received cell as an idle or unassigned cell, the header must exactly match the
respective pattern shown above (i.e., all five bytes are examined). The dropping of idle and/or unassigned cells
can be disabled through control register 1 (CR1) in the controller interface. A 24-bit counter is provided to count
the number of idle/unassigned cells that are dropped. Another 24-bit counter is provided to count the total
number of cells received that are not dropped and are placed in the receive output FIFO. When either of these
counters reaches maximum count, a bit is set in the status register and an interrupt is generated. These counters
are rollover counters (i.e., they roll over to zero after the maximum count occurs and an interrupt is generated).
After descrambling, the ATM cell is passed to the output buffer, which operates as a FIFO. The receive-cell
interface consists of the 8-/16-bit-wide output data (RD0-RD15), receive clock input (RCKI),
receive-read-enable (RRE) input, receive-cell-available (RXCLAV) output, and beginning of ATM cell indicator
(RXSOC) output. Output data is valid on the rising edge of RCKI when RRE is low and RXCLAV is high. The
loss-of-receive-data (LOSRD) alarm goes active in the controller interface and on an external pin when the
receive-output FIFO overflows. In this case, data placed into the FIFO is lost. The output FIFO holds three
complete ATM cells.
The RXCLAV output goes active when the output FIFO is capable of transferring a complete ATM cell. RXCLAV
goes inactive when the receive-output FIFO is empty and the data currently being output on RD0-RD15 is
invalid. The receive-cell interface is fully synchronous and all signals associated with the interface are either
sampled or valid on the rising edge of RCKI. The design goal for the interface is to operate at frequencies up
to 50 MHz over the worst-case V
CC
, worst-case process, and worst-case temperature.
The number of frames in which an event must occur to activate or deactivate the LAIS, LFERF, and PRDI signals is programmable for each signal,
independently, via the control registers. Default values are shown in the above text but can be changed to any whole number between one and
fifteen.
P
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