- 您現在的位置：買賣IC網 > PDF目錄385942 > TNETA1600 (Texas Instruments, Inc.) SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) PDF資料下載
參數資料
| 型號： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動柜員機接收器/發(fā)送器為622.08，麻省理工學院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動柜員機接收器/傳送器） |
| 文件頁數： | 31/54頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | TNETA1600 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
line-AIS consecutive-frame count (continued)
for seven consecutive frames and to deactivate upon the absence of the condition for two consecutive frames,
0111 0010 would be written to the register. The default value for LAIS activation and deactivation is five frames.
When a reset operation is performed, a value of 0101 0101 is placed in the register.
line-FERF consecutive-frame count
A line-FERF condition is detected in a frame as a 110 in bits 6–8 of the K2 byte. Any other pattern is not an LFERF
pattern. The input to this register represents the number of consecutive frames in which the condition must occur
for activation and, independently, the required number of consecutive frames without the condition for
deactivation of the LFERF bit in status register 2. As activation (and deactivation) may occur upon the detection
of a condition for up to 15 consecutive frames, the four most-significant bits of the register are used to represent
the number of consecutive frames (with the condition) required for activation while the four least-significant bits
represent the number of consecutive frames (without the condition) required for deactivation. For example, to
activate an interrupt through the status registers upon the detection of a condition for seven consecutive frames
and to deactivate upon the absence of the condition for two consecutive frames, 0111 0010 is written to the
register. The default value for LFERF activation and deactivation is five frames. When a reset operation is
performed, a value of 0101 0101 is placed in the register.
path-RDI consecutive-frame count
A path-RDI condition is detected in a frame as a 1 in bit 5 or bit 6 (or both) of the G1 byte. A 00 in these bits
indicates the absence of the condition. The input to this register represents the number of consecutive frames
in which the condition must occur for activation and, independently, the required number of consecutive frames
without the condition for deactivation of the PRDI bit in status register 3. As activation (and deactivation) may
occur upon the detection of a condition for up to 15 consecutive frames, the four most-significant bits of the
register are used to represent the number of consecutive frames (with the condition) required for activation while
the four least-significant bits represent the number of consecutive frames (without the condition) required for
deactivation. For example, to activate an interrupt through the status registers upon the detection of a condition
for seven consecutive frames and to deactivate upon the absence of the condition for two consecutive frames,
0111 0010 is written to the register. The default value for PRDI activation and deactivation is ten frames. When
a reset operation is performed, a value of 1010 1010 is placed in the register.
LOCA to path-RDI soak count
The input to this register provides a present to a counter that controls the amount of time, in increments of 125
μ
s
that a LOCA condition must be present before a path-RDI condition is sent via the outgoing G1 byte. The exact
amount of time required is not currently specified by any of the standard’s organizations. This register is preset
to a value of 32 (decimal) when a reset operation occurs. This corresponds to a soak time of 4 ms. The soak
time can be modified by writing a new value to this register. For instance, in order to set the value in the counter
to 1 ms, a value of eight (8 x 125
μ
s = 1 ms) is written in this register. However, the value has to be rewritten
if a reset operation occurs, as the present value revert to 4 ms. This feature automatically generates a path RDI
due to a LOCA condition when enabled (only if the appropriate bit is set in the control registers).
performance counters
The TNETA1600 contains several performance counters that provide running sums and statistics of various
parameters. Table 8 lists the performance counters accessible through the TNETA1600 controller interface. All
counters are 16-bit counters except the line-FEBE counter, the output ATM cell counter, and the discarded
idle/unassigned-cell counter, which are 24-bit counters.
All counters are read/write and their contents can be sampled or preset. The counters are reset to zero when
a device-reset operation occurs (i.e., when RESET goes low). The counters can also be effectively reset by
writing zeroes to the register. The counters do not reset when they are read.
P
相關PDF資料 |
PDF描述 |
|---|---|
| TNETA1610 | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| TNETA1611 | STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器) |
| TNETA1630 | 622.08-MHz Clock-Recovery Device(622.08-MHz時鐘發(fā)生裝置) |
| TO-252 | TO-252 (MP-3Z) |
| TODX2402 | FIBER OPTIC TRANSCEIVING MODULE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TNETA1600PCM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET FRAMER|QFP|160PIN|PLASTIC |
| TNETA1611PCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Transceiver |
| TNETA1622 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:622.08-MHz CLOCK-RECOVERY DEVICE |
| TNETA1622DW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock/Data Recovery |
| TNETA1630DW | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。